BibTeX record journals/ieicet/YamauchiSY07

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@article{DBLP:journals/ieicet/YamauchiSY07,
  author       = {Hiroyuki Yamauchi and
                  Toshikazu Suzuki and
                  Yoshinobu Yamagami},
  title        = {A 1R/1W {SRAM} Cell Design to Keep Cell Current and Area Saving against
                  Simultaneous Read/Write Disturbed Accesses},
  journal      = {{IEICE} Trans. Electron.},
  volume       = {90-C},
  number       = {4},
  pages        = {749--757},
  year         = {2007},
  url          = {https://doi.org/10.1093/ietele/e90-c.4.749},
  doi          = {10.1093/IETELE/E90-C.4.749},
  timestamp    = {Mon, 05 Feb 2024 20:20:44 +0100},
  biburl       = {https://dblp.org/rec/journals/ieicet/YamauchiSY07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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