BibTeX record conf/vlsid/VikramPMP18

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@inproceedings{DBLP:conf/vlsid/VikramPMP18,
  author       = {Sahu Sai Vikram and
                  Vibha Panty and
                  Mihir Mody and
                  Madhura Purnaprajna},
  title        = {TileNET: Scalable Architecture for High-Throughput Ternary Convolution
                  Neural Networks Using FPGAs},
  booktitle    = {31st International Conference on {VLSI} Design and 17th International
                  Conference on Embedded Systems, {VLSID} 2018, Pune, India, January
                  6-10, 2018},
  pages        = {461--462},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/VLSID.2018.113},
  doi          = {10.1109/VLSID.2018.113},
  timestamp    = {Fri, 24 Mar 2023 00:03:59 +0100},
  biburl       = {https://dblp.org/rec/conf/vlsid/VikramPMP18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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