BibTeX record conf/vlsic/ValaviRNV18

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@inproceedings{DBLP:conf/vlsic/ValaviRNV18,
  author    = {Hossein Valavi and
               Peter J. Ramadge and
               Eric Nestler and
               Naveen Verma},
  title     = {A Mixed-Signal Binarized Convolutional-Neural-Network Accelerator
               Integrating Dense Weight Storage and Multiplication for Reduced Data
               Movement},
  booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
               18-22, 2018},
  pages     = {141--142},
  publisher = {{IEEE}},
  year      = {2018},
  url       = {https://doi.org/10.1109/VLSIC.2018.8502421},
  doi       = {10.1109/VLSIC.2018.8502421},
  timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl    = {https://dblp.org/rec/conf/vlsic/ValaviRNV18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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