BibTeX record conf/vlsic/RovinskiZAGXTDA19

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@inproceedings{DBLP:conf/vlsic/RovinskiZAGXTDA19,
  author       = {Austin Rovinski and
                  Chun Zhao and
                  Khalid Al{-}Hawaj and
                  Paul Gao and
                  Shaolin Xie and
                  Christopher Torng and
                  Scott Davidson and
                  Aporva Amarnath and
                  Luis Vega and
                  Bandhav Veluri and
                  Anuj Rao and
                  Tutu Ajayi and
                  Julian Puscar and
                  Steve Dai and
                  Ritchie Zhao and
                  Dustin Richmond and
                  Zhiru Zhang and
                  Ian Galton and
                  Christopher Batten and
                  Michael B. Taylor and
                  Ronald G. Dreslinski},
  title        = {A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With
                  Mesh On-Chip Network and an All-Digital Synthesized {PLL} in 16nm
                  {CMOS}},
  booktitle    = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
  pages        = {30},
  publisher    = {{IEEE}},
  year         = {2019},
  url          = {https://doi.org/10.23919/VLSIC.2019.8778031},
  doi          = {10.23919/VLSIC.2019.8778031},
  timestamp    = {Tue, 12 Dec 2023 09:46:27 +0100},
  biburl       = {https://dblp.org/rec/conf/vlsic/RovinskiZAGXTDA19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}