BibTeX record conf/vlsic/ParkCNY15

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@inproceedings{DBLP:conf/vlsic/ParkCNY15,
  author       = {Sung{-}Yun Park and
                  Jihyun Cho and
                  Kyounghwan Na and
                  Euisik Yoon},
  title        = {Toward 1024-channel parallel neural recording: Modular {\(\Delta\)}-{\(\Delta\)}{\(\Sigma\)}
                  analog front-end architecture with 4.84fJ/C-s{\(\cdot\)}mm\({}^{\mbox{2}}\)
                  energy-area product},
  booktitle    = {Symposium on {VLSI} Circuits, {VLSIC} 2015, Kyoto, Japan, June 17-19,
                  2015},
  pages        = {112},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSIC.2015.7231344},
  doi          = {10.1109/VLSIC.2015.7231344},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsic/ParkCNY15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}