BibTeX record conf/vlsic/KatayamaMSH18

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@inproceedings{DBLP:conf/vlsic/KatayamaMSH18,
  author    = {Takato Katayama and
               Shiko Miyashita and
               Kazuki Sobue and
               Koichi Hamashita},
  title     = {A 1.25MS/S Two-Step Incremental {ADC} with 100DB {DR} and 110DB {SFDR}},
  booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
               18-22, 2018},
  pages     = {205--206},
  publisher = {{IEEE}},
  year      = {2018},
  url       = {https://doi.org/10.1109/VLSIC.2018.8502298},
  doi       = {10.1109/VLSIC.2018.8502298},
  timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl    = {https://dblp.org/rec/conf/vlsic/KatayamaMSH18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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