BibTeX record conf/vlsi-dat/WangWCR12

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@inproceedings{DBLP:conf/vlsi-dat/WangWCR12,
  author       = {Zheng Wang and
                  Xiao Wang and
                  Anupam Chattopadhyay and
                  Zoltan Endre Rakosi},
  title        = {{ASIC} synthesis using Architecture Description Language},
  booktitle    = {Proceedings of Technical Program of 2012 {VLSI} Design, Automation
                  and Test, {VLSI-DAT} 2012, Hsinchu, Taiwan, April 23-25, 2012},
  pages        = {1--4},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/VLSI-DAT.2012.6212614},
  doi          = {10.1109/VLSI-DAT.2012.6212614},
  timestamp    = {Wed, 16 Oct 2019 14:14:54 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi-dat/WangWCR12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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