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BibTeX record conf/slip/HeDHG09
@inproceedings{DBLP:conf/slip/HeDHG09, author = {Xu He and Sheqin Dong and Xianlong Hong and Satoshi Goto}, editor = {Chung{-}Kuan Cheng and Sherief Reda}, title = {Integrated interlayer via planning and pin assignment for 3D ICs}, booktitle = {The 11th International Workshop on System-Level Interconnect Prediction {(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings}, pages = {99--104}, publisher = {{ACM}}, year = {2009}, url = {https://doi.org/10.1145/1572471.1572488}, doi = {10.1145/1572471.1572488}, timestamp = {Tue, 06 Nov 2018 16:58:54 +0100}, biburl = {https://dblp.org/rec/conf/slip/HeDHG09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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