BibTeX record conf/sips/CheltonB06

download as .bib file

@inproceedings{DBLP:conf/sips/CheltonB06,
  author       = {William N. Chelton and
                  Mohammed Benaissa},
  title        = {High-Speed Pipelined {EGG} Processor on {FPGA}},
  booktitle    = {Proceedings of the {IEEE} Workshop on Signal Processing Systems, SiPS
                  2006, Proceedings, October 2-4, 2006, Banff, Alberta, Canada},
  pages        = {136--141},
  publisher    = {{IEEE}},
  year         = {2006},
  url          = {https://doi.org/10.1109/SIPS.2006.352569},
  doi          = {10.1109/SIPS.2006.352569},
  timestamp    = {Sun, 21 May 2017 00:20:17 +0200},
  biburl       = {https://dblp.org/rec/conf/sips/CheltonB06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
a service of  Schloss Dagstuhl - Leibniz Center for Informatics