BibTeX record conf/sbac-pad/WangJZLX16

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@inproceedings{DBLP:conf/sbac-pad/WangJZLX16,
  author       = {Zhe Wang and
                  Daniel A. Jim{\'{e}}nez and
                  Tao Zhang and
                  Gabriel H. Loh and
                  Yuan Xie},
  title        = {Building a Low Latency, Highly Associative {DRAM} Cache with the Buffered
                  Way Predictor},
  booktitle    = {28th International Symposium on Computer Architecture and High Performance
                  Computing, {SBAC-PAD} 2016, Los Angeles, CA, USA, October 26-28, 2016},
  pages        = {109--117},
  publisher    = {{IEEE} Computer Society},
  year         = {2016},
  url          = {https://doi.org/10.1109/SBAC-PAD.2016.22},
  doi          = {10.1109/SBAC-PAD.2016.22},
  timestamp    = {Thu, 23 Mar 2023 23:59:36 +0100},
  biburl       = {https://dblp.org/rec/conf/sbac-pad/WangJZLX16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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