BibTeX record conf/sac/QiuZWZWXX16

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@inproceedings{DBLP:conf/sac/QiuZWZWXX16,
  author       = {Keni Qiu and
                  Weigong Zhang and
                  Xiaoqiang Wu and
                  Xiaoyan Zhu and
                  Jing Wang and
                  Yuanchao Xu and
                  Chun Jason Xue},
  editor       = {Sascha Ossowski},
  title        = {Balanced loop retiming to effectively architect STT-RAM-based hybrid
                  cache for {VLIW} processors},
  booktitle    = {Proceedings of the 31st Annual {ACM} Symposium on Applied Computing,
                  Pisa, Italy, April 4-8, 2016},
  pages        = {1710--1716},
  publisher    = {{ACM}},
  year         = {2016},
  url          = {https://doi.org/10.1145/2851613.2851670},
  doi          = {10.1145/2851613.2851670},
  timestamp    = {Wed, 05 Aug 2020 07:51:35 +0200},
  biburl       = {https://dblp.org/rec/conf/sac/QiuZWZWXX16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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