BibTeX record conf/rtas/JiangYLKGSS16

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@inproceedings{DBLP:conf/rtas/JiangYLKGSS16,
  author       = {Yu Jiang and
                  Yixiao Yang and
                  Han Liu and
                  Hui Kong and
                  Ming Gu and
                  Jia{-}Guang Sun and
                  Lui Sha},
  title        = {From Stateflow Simulation to Verified Implementation: {A} Verification
                  Approach and {A} Real-Time Train Controller Design},
  booktitle    = {2016 {IEEE} Real-Time and Embedded Technology and Applications Symposium
                  (RTAS), Vienna, Austria, April 11-14, 2016},
  pages        = {231--241},
  publisher    = {{IEEE} Computer Society},
  year         = {2016},
  url          = {https://doi.org/10.1109/RTAS.2016.7461337},
  doi          = {10.1109/RTAS.2016.7461337},
  timestamp    = {Sat, 07 Oct 2023 21:26:26 +0200},
  biburl       = {https://dblp.org/rec/conf/rtas/JiangYLKGSS16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}