BibTeX record conf/isscc/SuSCCHTLLLWZJHL20

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@inproceedings{DBLP:conf/isscc/SuSCCHTLLLWZJHL20,
  author       = {Jian{-}Wei Su and
                  Xin Si and
                  Yen{-}Chi Chou and
                  Ting{-}Wei Chang and
                  Wei{-}Hsing Huang and
                  Yung{-}Ning Tu and
                  Ruhui Liu and
                  Pei{-}Jung Lu and
                  Ta{-}Wei Liu and
                  Jing{-}Hong Wang and
                  Zhixiao Zhang and
                  Hongwu Jiang and
                  Shanshi Huang and
                  Chung{-}Chuan Lo and
                  Ren{-}Shuo Liu and
                  Chih{-}Cheng Hsieh and
                  Kea{-}Tiong Tang and
                  Shyh{-}Shyuan Sheu and
                  Sih{-}Han Li and
                  Heng{-}Yuan Lee and
                  Shih{-}Chieh Chang and
                  Shimeng Yu and
                  Meng{-}Fan Chang},
  title        = {15.2 {A} 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T
                  {SRAM} Compute-in-Memory Macro for {AI} Edge Chips},
  booktitle    = {2020 {IEEE} International Solid- State Circuits Conference, {ISSCC}
                  2020, San Francisco, CA, USA, February 16-20, 2020},
  pages        = {240--242},
  publisher    = {{IEEE}},
  year         = {2020},
  url          = {https://doi.org/10.1109/ISSCC19947.2020.9062949},
  doi          = {10.1109/ISSCC19947.2020.9062949},
  timestamp    = {Tue, 21 Mar 2023 20:57:54 +0100},
  biburl       = {https://dblp.org/rec/conf/isscc/SuSCCHTLLLWZJHL20.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}