BibTeX record conf/islped/ChenWLK11

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@inproceedings{DBLP:conf/islped/ChenWLK11,
  author       = {Yiran Chen and
                  Weng{-}Fai Wong and
                  Hai Li and
                  Cheng{-}Kok Koh},
  editor       = {Naehyuck Chang and
                  Hiroshi Nakamura and
                  Koji Inoue and
                  Kenichi Osada and
                  Massimo Poncino},
  title        = {Processor caches with multi-level spin-transfer torque ram cells},
  booktitle    = {Proceedings of the 2011 International Symposium on Low Power Electronics
                  and Design, 2011, Fukuoka, Japan, August 1-3, 2011},
  pages        = {73--78},
  publisher    = {{IEEE/ACM}},
  year         = {2011},
  url          = {http://portal.acm.org/citation.cfm?id=2016826\&CFID=34981777\&CFTOKEN=25607807},
  timestamp    = {Mon, 04 Jul 2022 14:19:35 +0200},
  biburl       = {https://dblp.org/rec/conf/islped/ChenWLK11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}