BibTeX record conf/ises/KambleSPVK18

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@inproceedings{DBLP:conf/ises/KambleSPVK18,
  author       = {Chetan Kamble and
                  Siddharth R. K. and
                  Shivnarayan Patidar and
                  M. H. Vasantha and
                  Nithin Y. B. Kumar},
  title        = {Design of Area-Power-Delay Efficient Square Root Carry Select Adder},
  booktitle    = {{IEEE} International Symposium on Smart Electronic Systems, iSES 2018
                  (Formerly iNiS), Hyderabad, India, December 17-19, 2018},
  pages        = {80--85},
  publisher    = {{IEEE}},
  year         = {2018},
  url          = {https://doi.org/10.1109/iSES.2018.00026},
  doi          = {10.1109/ISES.2018.00026},
  timestamp    = {Mon, 03 Jan 2022 22:28:45 +0100},
  biburl       = {https://dblp.org/rec/conf/ises/KambleSPVK18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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