BibTeX record conf/iscc/TangSJYB16

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@inproceedings{DBLP:conf/iscc/TangSJYB16,
  author       = {Qiu Tang and
                  Majing Su and
                  Lei Jiang and
                  Jiajia Yang and
                  Xu Bai},
  title        = {A scalable architecture for low-latency market-data processing on
                  {FPGA}},
  booktitle    = {{IEEE} Symposium on Computers and Communication, {ISCC} 2016, Messina,
                  Italy, June 27-30, 2016},
  pages        = {597--603},
  publisher    = {{IEEE} Computer Society},
  year         = {2016},
  url          = {https://doi.org/10.1109/ISCC.2016.7543802},
  doi          = {10.1109/ISCC.2016.7543802},
  timestamp    = {Fri, 24 Mar 2023 00:03:16 +0100},
  biburl       = {https://dblp.org/rec/conf/iscc/TangSJYB16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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