BibTeX record conf/iscas/SuWT14

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@inproceedings{DBLP:conf/iscas/SuWT14,
  author       = {Hung{-}Cheng Su and
                  Tsung{-}Han Wu and
                  Chun{-}Jen Tsai},
  title        = {Temporal multithreading architecture design for a Java processor},
  booktitle    = {{IEEE} International Symposium on Circuits and Systemss, {ISCAS} 2014,
                  Melbourne, Victoria, Australia, June 1-5, 2014},
  pages        = {2201--2204},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/ISCAS.2014.6865606},
  doi          = {10.1109/ISCAS.2014.6865606},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/iscas/SuWT14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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