BibTeX record conf/hldvt/KimCSY08

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@inproceedings{DBLP:conf/hldvt/KimCSY08,
  author       = {Dusung Kim and
                  Maciej J. Ciesielski and
                  Kyuho Shim and
                  Seiyang Yang},
  title        = {Temporal parallel gate-level timing simulation},
  booktitle    = {{IEEE} International High Level Design Validation and Test Workshop,
                  {HLDVT} 2008, Incline Village, NV, USA, November 19-21, 2008},
  pages        = {111--116},
  publisher    = {{IEEE} Computer Society},
  year         = {2008},
  url          = {https://doi.org/10.1109/HLDVT.2008.4695886},
  doi          = {10.1109/HLDVT.2008.4695886},
  timestamp    = {Wed, 16 Oct 2019 14:14:57 +0200},
  biburl       = {https://dblp.org/rec/conf/hldvt/KimCSY08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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