BibTeX record conf/glvlsi/ChenTKHR94

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@inproceedings{DBLP:conf/glvlsi/ChenTKHR94,
  author       = {Yulin Chen and
                  Wei Kang Tsai and
                  Fadi J. Kurdahi and
                  Tzong{-}Dar Her and
                  Champaka Ramachandran},
  title        = {A performance driven logic synthesis system using delay estimator},
  booktitle    = {Fourth Great Lakes Symposium on Design Automation of High Performance
                  {VLSI} Systems, {GLSV} '94, Notre Dame, IN, USA, March 4-5, 1994},
  pages        = {88--92},
  publisher    = {{IEEE}},
  year         = {1994},
  url          = {https://doi.org/10.1109/GLSV.1994.289990},
  doi          = {10.1109/GLSV.1994.289990},
  timestamp    = {Wed, 16 Oct 2019 14:14:57 +0200},
  biburl       = {https://dblp.org/rec/conf/glvlsi/ChenTKHR94.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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