BibTeX record conf/esscirc/ChenSNLC0R19

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@inproceedings{DBLP:conf/esscirc/ChenSNLC0R19,
  author       = {Yongzhen Chen and
                  Xingchen Shen and
                  Zhekan Ni and
                  Jingchao Lan and
                  Chixiao Chen and
                  Fan Ye and
                  Junyan Ren},
  title        = {A 625MS/s, 12-Bit, {SAR} Assisted Pipeline {ADC} with Effective Gain
                  Analysis for Inter-stage Ringamps},
  booktitle    = {45th {IEEE} European Solid State Circuits Conference, {ESSCIRC} 2019,
                  Cracow, Poland, September 23-26, 2019},
  pages        = {197--200},
  publisher    = {{IEEE}},
  year         = {2019},
  url          = {https://doi.org/10.1109/ESSCIRC.2019.8902892},
  doi          = {10.1109/ESSCIRC.2019.8902892},
  timestamp    = {Tue, 26 Nov 2019 12:08:14 +0100},
  biburl       = {https://dblp.org/rec/conf/esscirc/ChenSNLC0R19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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