BibTeX record conf/codes/HameedBH13

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@inproceedings{DBLP:conf/codes/HameedBH13,
  author       = {Fazal Hameed and
                  Lars Bauer and
                  J{\"{o}}rg Henkel},
  title        = {Reducing inter-core cache contention with an adaptive bank mapping
                  policy in {DRAM} cache},
  booktitle    = {Proceedings of the International Conference on Hardware/Software Codesign
                  and System Synthesis, {CODES+ISSS} 2013, Montreal, QC, Canada, September
                  29 - October 4, 2013},
  pages        = {1:1--1:8},
  publisher    = {{IEEE}},
  year         = {2013},
  url          = {https://doi.org/10.1109/CODES-ISSS.2013.6658988},
  doi          = {10.1109/CODES-ISSS.2013.6658988},
  timestamp    = {Mon, 05 Feb 2024 20:28:07 +0100},
  biburl       = {https://dblp.org/rec/conf/codes/HameedBH13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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