BibTeX record conf/ats/AsadaWHMKKSWQ15

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@inproceedings{DBLP:conf/ats/AsadaWHMKKSWQ15,
  author    = {K. Asada and
               Xiaoqing Wen and
               Stefan Holst and
               Kohei Miyase and
               Seiji Kajihara and
               Michael A. Kochte and
               Eric Schneider and
               Hans{-}Joachim Wunderlich and
               J. Qian},
  title     = {Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding
               False Capture Failures and Reducing Clock Stretch},
  booktitle = {24th {IEEE} Asian Test Symposium, {ATS} 2015, Mumbai, India, November
               22-25, 2015},
  pages     = {103--108},
  year      = {2015},
  crossref  = {DBLP:conf/ats/2015},
  url       = {https://doi.org/10.1109/ATS.2015.25},
  doi       = {10.1109/ATS.2015.25},
  timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/ats/AsadaWHMKKSWQ15},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/ats/2015,
  title     = {24th {IEEE} Asian Test Symposium, {ATS} 2015, Mumbai, India, November
               22-25, 2015},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/7421875/proceeding},
  isbn      = {978-1-4673-9739-1},
  timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/ats/2015},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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