BibTeX record conf/async/MekieCSVT06

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@inproceedings{DBLP:conf/async/MekieCSVT06,
  author    = {Joycee Mekie and
               Supratik Chakraborty and
               Dinesh K. Sharma and
               Girish Venkataramani and
               P. S. Thiagarajan},
  title     = {Interface Design for Rationally Clocked {GALS} Systems},
  booktitle = {12th {IEEE} International Symposium on Asynchronous Circuits and Systems
               {(ASYNC} 2006), 13-15 March 2006, Grenoble, France},
  pages     = {160--171},
  year      = {2006},
  crossref  = {DBLP:conf/async/2006},
  url       = {https://doi.org/10.1109/ASYNC.2006.19},
  doi       = {10.1109/ASYNC.2006.19},
  timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/async/MekieCSVT06},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/async/2006,
  title     = {12th {IEEE} International Symposium on Asynchronous Circuits and Systems
               {(ASYNC} 2006), 13-15 March 2006, Grenoble, France},
  publisher = {{IEEE} Computer Society},
  year      = {2006},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/10635/proceeding},
  isbn      = {0-7695-2498-2},
  timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/async/2006},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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