BibTeX record conf/asscc/ChenZZZSS17

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@inproceedings{DBLP:conf/asscc/ChenZZZSS17,
  author       = {Peng Chen and
                  Feifei Zhang and
                  Zhirui Zong and
                  Hao Zheng and
                  Teerachot Siriburanon and
                  Robert Bogdan Staszewski},
  title        = {A 15-{\(\mu\)}W, 103-fs step, 5-bit capacitor-DAC-based constant-slope
                  digital-to-time converter in 28nm {CMOS}},
  booktitle    = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2017, Seoul,
                  Korea (South), November 6-8, 2017},
  pages        = {93--96},
  publisher    = {{IEEE}},
  year         = {2017},
  url          = {https://doi.org/10.1109/ASSCC.2017.8240224},
  doi          = {10.1109/ASSCC.2017.8240224},
  timestamp    = {Sun, 02 Oct 2022 15:55:07 +0200},
  biburl       = {https://dblp.org/rec/conf/asscc/ChenZZZSS17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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