BibTeX record conf/aspdac/NiitsuHHOSKYK13

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@inproceedings{DBLP:conf/aspdac/NiitsuHHOSKYK13,
  author    = {Kiichi Niitsu and
               Naohiro Harigai and
               Daiki Hirabayashi and
               Daiki Oki and
               Masato Sakurai and
               Osamu Kobayashi and
               Takahiro J. Yamaguchi and
               Haruo Kobayashi},
  title     = {Design of a clock jitter reduction circuit using gated phase blending
               between self-delayed clock edges},
  booktitle = {18th Asia and South Pacific Design Automation Conference, {ASP-DAC}
               2013, Yokohama, Japan, January 22-25, 2013},
  pages     = {103--104},
  year      = {2013},
  crossref  = {DBLP:conf/aspdac/2013},
  url       = {https://doi.org/10.1109/ASPDAC.2013.6509577},
  doi       = {10.1109/ASPDAC.2013.6509577},
  timestamp = {Fri, 26 May 2017 00:50:29 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/aspdac/NiitsuHHOSKYK13},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/aspdac/2013,
  title     = {18th Asia and South Pacific Design Automation Conference, {ASP-DAC}
               2013, Yokohama, Japan, January 22-25, 2013},
  publisher = {{IEEE}},
  year      = {2013},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6507004},
  isbn      = {978-1-4673-3029-9},
  timestamp = {Fri, 03 May 2013 13:35:45 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/aspdac/2013},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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