BibTeX record conf/asicon/GeZ0W017

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@inproceedings{DBLP:conf/asicon/GeZ0W017,
  author       = {Xiang Ge and
                  Hengliang Zhu and
                  Fan Yang and
                  Lingli Wang and
                  Xuan Zeng},
  editor       = {Yajie Qin and
                  Zhiliang Hong and
                  Ting{-}Ao Tang},
  title        = {Parallel sparse {LU} decomposition using {FPGA} with an efficient
                  cache architecture},
  booktitle    = {12th {IEEE} International Conference on ASIC, {ASICON} 2017, Guiyang,
                  China, October 25-28, 2017},
  pages        = {259--262},
  publisher    = {{IEEE}},
  year         = {2017},
  url          = {https://doi.org/10.1109/ASICON.2017.8252462},
  doi          = {10.1109/ASICON.2017.8252462},
  timestamp    = {Wed, 16 Oct 2019 14:14:56 +0200},
  biburl       = {https://dblp.org/rec/conf/asicon/GeZ0W017.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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