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ORCIDP. Sadayappan
- > Home > Persons > P. Sadayappan
Publications
- 2011
[c172]Louis-Noël Pouchet, Uday Bondhugula, Cédric Bastoul, Albert Cohen, J. Ramanujam
, P. Sadayappan, Nicolas Vasilache:
Loop transformations: convexity, pruning and optimization. POPL 2011: 549-562- 2010
- [c162]Louis-Noël Pouchet, Uday Bondhugula, Cédric Bastoul, Albert Cohen, J. Ramanujam, P. Sadayappan:
Combined Iterative and Model-driven Optimization in an Automatic Parallelization Framework. SC 2010: 1-11 - 2009
- [c160]Qingda Lu, Christophe Alias, Uday Bondhugula, Thomas Henretty, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan, Yongjian Chen, Haibo Lin, Tin-Fook Ngai:
Data Layout Transformation for Enhancing Data Locality on NUCA Chip Multiprocessors. PACT 2009: 348-357 - [c155]Muthu Manikandan Baskaran, Nagavijayalakshmi Vydyanathan, Uday Bondhugula, J. Ramanujam, Atanas Rountev, P. Sadayappan:
Compiler-assisted dynamic scheduling for effective parallelization of loop nests on multicore processors. PPoPP 2009: 219-228 - 2008
- [c152]Uday Bondhugula, Muthu Manikandan Baskaran, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan:
Automatic Transformations for Communication-Minimized Parallelization and Locality Optimization in the Polyhedral Model. CC 2008: 132-146 - [c144]Muthu Manikandan Baskaran, Uday Bondhugula, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan:
A compiler framework for optimization of affine loop nests for gpgpus. ICS 2008: 225-234 - [c143]Uday Bondhugula, Muthu Manikandan Baskaran, Albert Hartono, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan:
Towards effective automatic parallelization for multicore systems. IPDPS 2008: 1-5 - [c141]Uday Bondhugula, Albert Hartono, J. Ramanujam, P. Sadayappan:
A practical automatic polyhedral parallelizer and locality optimizer. PLDI 2008: 101-113 - [c140]Muthu Manikandan Baskaran, Uday Bondhugula, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan:
Automatic data movement and computation mapping for multi-level parallel architectures with explicitly managed memories. PPoPP 2008: 1-10 - 2007
- [c131]Sriram Krishnamoorthy, Muthu Manikandan Baskaran, Uday Bondhugula, J. Ramanujam, Atanas Rountev, P. Sadayappan:
Effective automatic parallelization of stencil computations. PLDI 2007: 235-244 - [c130]Uday Bondhugula, J. Ramanujam, P. Sadayappan:
Automatic mapping of nested loops to FPGAS. PPoPP 2007: 101-111 - 2006
- [c125]Uday Bondhugula, Ananth Devulapalli, James Dinan, Joseph Fernando, Pete Wyckoff, Eric Stahlberg, P. Sadayappan:
Hardware/Software Integration for FPGA-based All-Pairs Shortest-Paths. FCCM 2006: 152-164 - [c120]Uday Bondhugula, Ananth Devulapalli, Joseph Fernando, Pete Wyckoff, P. Sadayappan:
Parallel FPGA-based all-pairs shortest-paths in a directed graph. IPDPS 2006
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