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ORCIDIrith Pomeranz
Person information
- affiliation: Purdue University, School of Electrical and Computer Engineering, West Lafayette, IN, USA
- affiliation: University of Iowa, Department of Electrical and Computer Engineering, Iowa City, IA, USA
- affiliation (PhD 1989): Technion, Department of Electrical Engineering, Israel
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Journal Articles
- 2024
[j319]Irith Pomeranz
:
Longest Path Selection Based on Path Identifiers. IEEE Access 12: 14512-14520 (2024)- [j318]Irith Pomeranz:
Sharing of Topped-Off Compressed Test Sets Among Logic Blocks. IEEE Access 12: 49895-49903 (2024) - [j317]Irith Pomeranz:
Dynamic Test Compaction of a Compressed Test Set Shared Among Logic Blocks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(1): 394-402 (2024) - [j316]Jerin Joe, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski:
Generation of Two-Cycle Tests for Structurally Similar Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(2): 694-703 (2024) - [j315]Irith Pomeranz:
Test Insertion for Dynamic Test Compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(4): 1302-1306 (2024) - [j314]Irith Pomeranz:
Testability Evaluation for Local Design Modifications. IEEE Trans. Very Large Scale Integr. Syst. 32(1): 195-199 (2024) - [j313]Irith Pomeranz:
Bit-Complemented Test Data to Replace the Tail of a Fault Coverage Curve. IEEE Trans. Very Large Scale Integr. Syst. 32(4): 609-618 (2024) - 2023
- [j312]Irith Pomeranz:
Storage and Counter Based Logic Built-In Self-Test. IEEE Access 11: 139335-139344 (2023) - [j311]Irith Pomeranz:
Topping Off Test Sets Under Bounded Transparent Scan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(1): 341-345 (2023) - [j310]Irith Pomeranz:
Functionally Possible Scan-Based Test Set as a Dual of a Compressed Multicycle Test Set. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(4): 1336-1345 (2023) - [j309]Irith Pomeranz:
Estimating the Number of Extra Tests During Iterative Test Generation for Single-Cycle Gate-Exhaustive Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(8): 2752-2760 (2023) - [j308]Irith Pomeranz:
Storage-Based Logic Built-In Self-Test With Cyclic Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(9): 3118-3122 (2023) - [j307]Irith Pomeranz:
Partially Specified Output Response for Reduced Fail Data Volume. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(9): 3123-3127 (2023) - [j306]Irith Pomeranz:
Path Unselection for Path Delay Fault Test Generation. IEEE Trans. Very Large Scale Integr. Syst. 31(2): 267-275 (2023) - [j305]Irith Pomeranz:
Diagnostic Test Point Insertion and Test Compaction. IEEE Trans. Very Large Scale Integr. Syst. 31(2): 276-285 (2023) - [j304]Irith Pomeranz:
Sharing of Compressed Tests Among Logic Blocks. IEEE Trans. Very Large Scale Integr. Syst. 31(4): 421-430 (2023) - [j303]Irith Pomeranz:
Test Data Compression for Transparent-Scan Sequences. IEEE Trans. Very Large Scale Integr. Syst. 31(4): 601-605 (2023) - [j302]Irith Pomeranz:
Storage-Based Logic Built-In Self-Test With Partitioned Deterministic Compressed Tests. IEEE Trans. Very Large Scale Integr. Syst. 31(9): 1259-1268 (2023) - [j301]Irith Pomeranz:
Dummy Faulty Units for Reduced Fail Data Volume From Logic Faults. IEEE Trans. Very Large Scale Integr. Syst. 31(11): 1754-1762 (2023) - 2022
- [j300]Irith Pomeranz:
Efficient Identification of Undetectable Two-Cycle Gate-Exhaustive Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(3): 776-783 (2022) - [j299]Irith Pomeranz:
Static Test Compaction Using Independent Suffixes of a Transparent-Scan Sequence. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(4): 1130-1141 (2022) - [j298]Irith Pomeranz:
Multicycle Tests With Fault Detection Test Data for Improved Logic Diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1587-1591 (2022) - [j297]Irith Pomeranz:
GEPDFs: Path Delay Faults Based on Two-Cycle Gate-Exhaustive Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7): 2315-2322 (2022) - [j296]Irith Pomeranz:
Storage-Based Logic Built-in Self-Test With Multicycle Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10): 3553-3557 (2022) - [j295]Irith Pomeranz:
Pass/Fail Data for Logic Diagnosis Under Bounded Transparent Scan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4862-4872 (2022) - [j294]Irith Pomeranz:
Wrapping Paths of Undetected Transition Faults With Two-Cycle Gate-Exhaustive Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5635-5643 (2022) - [j293]Irith Pomeranz:
Increasing the Fault Coverage of a Truncated Test Set. ACM Trans. Design Autom. Electr. Syst. 27(6): 54:1-54:16 (2022) - [j292]Irith Pomeranz:
Preponing Fault Detections for Test Compaction Under Transparent Scan. IEEE Trans. Very Large Scale Integr. Syst. 30(10): 1543-1547 (2022) - [j291]Irith Pomeranz:
Test Sequences for Faults in the Scan Logic. IEEE Trans. Very Large Scale Integr. Syst. 30(10): 1568-1572 (2022) - [j290]Irith Pomeranz:
Functional Test Sequences as a Source for Partially Functional Launch-on-Shift Tests. IEEE Trans. Very Large Scale Integr. Syst. 30(11): 1803-1807 (2022) - 2021
- [j289]Irith Pomeranz:
Maximal Independent Fault Set for Gate-Exhaustive Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(3): 598-602 (2021) - [j288]Irith Pomeranz:
PRESERVE: Static Test Compaction that Preserves Individual Numbers of Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(4): 803-807 (2021) - [j287]Irith Pomeranz:
Padding of LFSR Seeds for Reduced Input Test Data Volume. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(5): 1004-1008 (2021) - [j286]Irith Pomeranz, M. Enamul Amyeen:
Hybrid Pass/Fail and Full Fail Data for Reduced Fail Data Volume. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(8): 1711-1720 (2021) - [j285]Irith Pomeranz:
Storage-Based Built-In Self-Test for Gate-Exhaustive Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(10): 2189-2193 (2021) - [j284]Irith Pomeranz, M. Enamul Amyeen:
Logic Diagnosis with Hybrid Fail Data. ACM Trans. Design Autom. Electr. Syst. 26(3): 19:1-19:13 (2021) - [j283]Irith Pomeranz:
Covering Test Holes of Functional Broadside Tests. ACM Trans. Design Autom. Electr. Syst. 26(3): 23:1-23:15 (2021) - [j282]Irith Pomeranz:
Equivalent Faults under Launch-on-Shift (LOS) Tests with Equal Primary Input Vectors. ACM Trans. Design Autom. Electr. Syst. 26(4): 25:1-25:15 (2021) - [j281]Irith Pomeranz:
Partitioning Functional Test Sequences Into Multicycle Functional Broadside Tests. IEEE Trans. Very Large Scale Integr. Syst. 29(1): 89-99 (2021) - [j280]Irith Pomeranz:
Test Compaction by Backward and Forward Extension of Multicycle Tests. IEEE Trans. Very Large Scale Integr. Syst. 29(1): 242-246 (2021) - [j279]Irith Pomeranz, Xijiang Lin:
Single Test Type to Replace Broadside and Skewed-Load Tests for Transition Faults. IEEE Trans. Very Large Scale Integr. Syst. 29(2): 423-433 (2021) - [j278]Irith Pomeranz:
Functional Constraints in the Selection of Two-Cycle Gate-Exhaustive Faults for Test Generation. IEEE Trans. Very Large Scale Integr. Syst. 29(7): 1500-1504 (2021) - 2020
- [j277]Irith Pomeranz:
LFSR-based generation of boundary-functional broadside tests. IET Comput. Digit. Tech. 14(2): 61-68 (2020) - [j276]Irith Pomeranz:
Multicycle Broadside and Skewed-Load Tests for Test Compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(1): 262-266 (2020) - [j275]Irith Pomeranz:
Reverse Low-Power Broadside Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(3): 742-746 (2020) - [j274]Irith Pomeranz:
Switching Activity of Faulty Circuits in Presence of Multiple Transition Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(4): 936-945 (2020) - [j273]Irith Pomeranz:
Broadside Tests for Transition and Stuck-At Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(8): 1739-1743 (2020) - [j272]Irith Pomeranz:
Globally Functional Transparent-Scan Sequences. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 3012-3022 (2020) - [j271]Irith Pomeranz:
New Targets for Diagnostic Test Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 3035-3043 (2020) - [j270]Irith Pomeranz:
Functional Broadside Tests Under Broadcast Scan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 3139-3143 (2020) - [j269]Irith Pomeranz:
Direct Computation of LFSR-Based Stored Tests for Broadside and Skewed-Load Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 5238-5246 (2020) - [j268]Irith Pomeranz, Srikanth Venkataraman:
LFSR-Based Test Generation for Reduced Fail Data Volume. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 5261-5266 (2020) - [j267]Irith Pomeranz:
Target Faults for Test Compaction Based on Multicycle Tests. ACM Trans. Design Autom. Electr. Syst. 25(2): 18:1-18:14 (2020) - [j266]Irith Pomeranz:
Selection of Primary Output Vectors to Observe Under Multicycle Tests. IEEE Trans. Very Large Scale Integr. Syst. 28(1): 156-162 (2020) - [j265]Irith Pomeranz:
Extra Clocking of LFSR Seeds for Improved Path Delay Fault Coverage. IEEE Trans. Very Large Scale Integr. Syst. 28(2): 544-552 (2020) - [j264]Irith Pomeranz:
RETRO: Reintroducing Tests for Improved Reverse Order Fault Simulation. IEEE Trans. Very Large Scale Integr. Syst. 28(8): 1930-1934 (2020) - [j263]Irith Pomeranz:
Broad-Brush Compaction for Sequential Test Generation. IEEE Trans. Very Large Scale Integr. Syst. 28(8): 1940-1944 (2020) - 2019
- [j262]Irith Pomeranz:
Updating the sets of target faults during test generation for multiple fault models. IET Comput. Digit. Tech. 13(5): 369-375 (2019) - [j261]Irith Pomeranz:
Diagnostic Test Generation That Addresses Diagnostic Holes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(2): 335-344 (2019) - [j260]Irith Pomeranz:
LFSR-Based Test Generation for Path Delay Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(2): 345-353 (2019) - [j259]Irith Pomeranz:
Skewed-Load Tests for Transition and Stuck-at Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(10): 1969-1973 (2019) - [j258]Irith Pomeranz:
Invisible-Scan: A Design-for-Testability Approach for Functional Test Sequences. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(12): 2357-2365 (2019) - [j257]Irith Pomeranz:
Boundary-Functional Broadside and Skewed-Load Tests. ACM Trans. Design Autom. Electr. Syst. 24(1): 7:1-7:20 (2019) - [j256]Irith Pomeranz:
Incomplete Tests for Undetectable Faults to Improve Test Set Quality. ACM Trans. Design Autom. Electr. Syst. 24(2): 23:1-23:13 (2019) - [j255]Naixing Wang, Irith Pomeranz, Sudhakar M. Reddy, Arani Sinha, Srikanth Venkataraman:
Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design. ACM Trans. Design Autom. Electr. Syst. 24(4): 42:1-42:19 (2019) - [j254]Irith Pomeranz:
Test Compaction by Test Removal Under Transparent Scan. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 496-500 (2019) - [j253]Irith Pomeranz:
Extracting a Close-to-Minimum Multicycle Functional Broadside Test Set From a Functional Test Sequence. IEEE Trans. Very Large Scale Integr. Syst. 27(6): 1428-1437 (2019) - [j252]Irith Pomeranz:
Test Scores for Improving the Accuracy of Logic Diagnosis for Multiple Defects. IEEE Trans. Very Large Scale Integr. Syst. 27(7): 1720-1724 (2019) - [j251]Irith Pomeranz:
Extended Transparent-Scan. IEEE Trans. Very Large Scale Integr. Syst. 27(9): 2096-2104 (2019) - [j250]Irith Pomeranz:
Padding of Multicycle Broadside and Skewed-Load Tests. IEEE Trans. Very Large Scale Integr. Syst. 27(11): 2587-2595 (2019) - 2018
- [j249]Irith Pomeranz:
On-chip generation of primary input sequences for multicycle functional broadside tests. IET Comput. Digit. Tech. 12(3): 80-86 (2018) - [j248]Irith Pomeranz:
Static test compaction procedure for large pools of multicycle functional broadside tests. IET Comput. Digit. Tech. 12(5): 233-240 (2018) - [j247]Irith Pomeranz:
Improving the Diagnosability of Scan Chain Faults Under Transparent-Scan by Observation Points. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(6): 1278-1287 (2018) - [j246]Irith Pomeranz:
An Initialization Process to Support Online Testing Based on Output Comparison for Identical Finite-State Machines. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(7): 1494-1504 (2018) - [j245]Irith Pomeranz:
Autonomous Multicycle Tests With Low Storage and Test Application Time Overheads. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(9): 1881-1892 (2018) - [j244]Irith Pomeranz:
Partially Invariant Patterns for LFSR-Based Generation of Close-to-Functional Broadside Tests. ACM Trans. Design Autom. Electr. Syst. 23(4): 53:1-53:18 (2018) - [j243]Irith Pomeranz:
Dynamically Determined Preferred Values and a Design-for-Testability Approach for Multiplexer Select Inputs under Functional Test Sequences. ACM Trans. Design Autom. Electr. Syst. 23(5): 59:1-59:16 (2018) - [j242]Irith Pomeranz:
Selecting Functional Test Sequences for Defect Diagnosis. IEEE Trans. Very Large Scale Integr. Syst. 26(10): 2160-2164 (2018) - [j241]Irith Pomeranz:
Observation Points on State Variables for the Compaction of Multicycle Tests. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2567-2571 (2018) - 2017
- [j240]Irith Pomeranz:
Reconstruction of a functional test sequence for increased fault coverage. IET Comput. Digit. Tech. 11(3): 91-97 (2017) - [j239]Irith Pomeranz:
Metric for the ability of functional capture cycles to ensure functional operation conditions. IET Comput. Digit. Tech. 11(3): 100-106 (2017) - [j238]Marco Gaudesi, Irith Pomeranz, Matteo Sonza Reorda, Giovanni Squillero:
New Techniques to Reduce the Execution Time of Functional Test Programs. IEEE Trans. Computers 66(7): 1268-1273 (2017) - [j237]Irith Pomeranz:
Sequential Test Generation Based on Preferred Primary Input Cubes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(2): 351-355 (2017) - [j236]Irith Pomeranz:
LFSR-Based Generation of Multicycle Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(3): 503-507 (2017) - [j235]Irith Pomeranz:
Identifying Biases of a Defect Diagnosis Procedure. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(7): 1215-1225 (2017) - [j234]Irith Pomeranz:
Clock Sequences for Increasing the Fault Coverage of Functional Test Sequences. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(7): 1231-1235 (2017) - [j233]Irith Pomeranz:
Restoration-Based Merging of Functional Test Sequences. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(10): 1739-1749 (2017) - [j232]Irith Pomeranz:
Close-to-Functional Broadside Tests With a Safety Margin. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(12): 2139-2143 (2017) - [j231]Irith Pomeranz:
Computation of Seeds for LFSR-Based n-Detection Test Generation. ACM Trans. Design Autom. Electr. Syst. 22(2): 29:1-29:13 (2017) - [j230]Irith Pomeranz:
Generation of Transparent-Scan Sequences for Diagnosis of Scan Chain Faults. ACM Trans. Design Autom. Electr. Syst. 22(3): 43:1-43:17 (2017) - [j229]Irith Pomeranz, M. Enamul Amyeen, Srikanth Venkataraman:
Test Modification for Reduced Volumes of Fail Data. ACM Trans. Design Autom. Electr. Syst. 22(4): 67:1-67:17 (2017) - [j228]Shraddha Bodhe, Irith Pomeranz, M. Enamul Amyeen, Srikanth Venkataraman:
Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction. IEEE Trans. Very Large Scale Integr. Syst. 25(4): 1497-1505 (2017) - [j227]Irith Pomeranz:
Selecting Replacements for Undetectable Path Delay Faults. IEEE Trans. Very Large Scale Integr. Syst. 25(6): 1988-1992 (2017) - 2016
- [j226]Irith Pomeranz:
Static test compaction for circuits with multiple independent scan chains. IET Comput. Digit. Tech. 10(1): 12-17 (2016) - [j225]Irith Pomeranz:
Improving the accuracy of defect diagnosis by adding and removing tests. IET Comput. Digit. Tech. 10(2): 47-53 (2016) - [j224]Irith Pomeranz:
Combined input test data volume reduction for mixed broadside and skewed-load test sets. IET Comput. Digit. Tech. 10(3): 138-145 (2016) - [j223]Irith Pomeranz:
Improving the Accuracy of Defect Diagnosis with Multiple Sets of Candidate Faults. IEEE Trans. Computers 65(7): 2332-2338 (2016) - [j222]Irith Pomeranz:
LFSR-Based Generation of Partially-Functional Broadside Tests. IEEE Trans. Computers 65(8): 2659-2664 (2016) - [j221]Irith Pomeranz:
Balancing the Numbers of Detected Faults for Improved Test Set Quality. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(2): 337-341 (2016) - [j220]Irith Pomeranz:
Static Test Compaction for Functional Test Sequences With Restoration of Functional Switching Activity. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(10): 1755-1762 (2016) - [j219]Irith Pomeranz:
Design-for-Testability for Functional Broadside Tests under Primary Input Constraints. ACM Trans. Design Autom. Electr. Syst. 21(2): 35:1-35:18 (2016) - [j218]Irith Pomeranz:
N-Detection Test Sets for Circuits with Multiple Independent Scan Chains. ACM Trans. Design Autom. Electr. Syst. 21(4): 68:1-68:15 (2016) - [j217]Irith Pomeranz:
Periodic Scan-In States to Reduce the Input Test Data Volume for Partially Functional Broadside Tests. ACM Trans. Design Autom. Electr. Syst. 22(1): 7:1-7:22 (2016) - [j216]Shraddha Bodhe, M. Enamul Amyeen, Irith Pomeranz, Srikanth Venkataraman:
Diagnostic Fail Data Minimization Using an N-Cover Algorithm. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 1198-1202 (2016) - [j215]Irith Pomeranz:
Computing Seeds for LFSR-Based Test Generation From Nontest Cubes. IEEE Trans. Very Large Scale Integr. Syst. 24(6): 2392-2396 (2016) - [j214]Irith Pomeranz:
A Test Selection Procedure for Improving the Accuracy of Defect Diagnosis. IEEE Trans. Very Large Scale Integr. Syst. 24(8): 2759-2767 (2016) - 2015
- [j213]Irith Pomeranz:
Use of input necessary assignments for test generation based on merging of test cubes. IET Comput. Digit. Tech. 9(2): 106-112 (2015) - [j212]Irith Pomeranz:
Piecewise-Functional Broadside Tests Based on Reachable States. IEEE Trans. Computers 64(8): 2415-2420 (2015) - [j211]Irith Pomeranz:
Two-Dimensional Static Test Compaction for Functional Test Sequences. IEEE Trans. Computers 64(10): 3009-3015 (2015) - [j210]Irith Pomeranz:
Test Vector Omission for Fault Coverage Improvement of Functional Test Sequences. IEEE Trans. Computers 64(11): 3317-3321 (2015) - [j209]Irith Pomeranz:
A Multicycle Test Set Based on a Two-Cycle Test Set With Constant Primary Input Vectors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(7): 1124-1132 (2015) - [j208]Irith Pomeranz:
Computation of Seeds for LFSR-Based Diagnostic Test Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(12): 2004-2012 (2015) - [j207]Irith Pomeranz:
A Generalized Definition of Unnecessary Test Vectors in Functional Test Sequences. ACM Trans. Design Autom. Electr. Syst. 20(2): 29:1-29:13 (2015) - [j206]Irith Pomeranz:
FOLD: Extreme Static Test Compaction by Folding of Functional Test Sequences. ACM Trans. Design Autom. Electr. Syst. 20(4): 57:1-57:19 (2015) - [j205]Irith Pomeranz:
Enhanced Test Compaction for Multicycle Broadside Tests by Using State Complementation. ACM Trans. Design Autom. Electr. Syst. 21(1): 13:1-13:20 (2015) - [j204]Irith Pomeranz:
Skewed-Load Test Cubes Based on Functional Broadside Tests for a Low-Power Test Set. IEEE Trans. Very Large Scale Integr. Syst. 23(3): 593-597 (2015) - [j203]Irith Pomeranz:
Static Test Compaction for Low-Power Test Sets by Increasing the Switching Activity. IEEE Trans. Very Large Scale Integr. Syst. 23(9): 1936-1940 (2015) - [j202]Irith Pomeranz:
Modeling a Set of Functional Test Sequences as a Single Sequence for Test Compaction. IEEE Trans. Very Large Scale Integr. Syst. 23(11): 2629-2638 (2015) - [j201]Irith Pomeranz:
Test Compaction by Sharing of Functional Test Sequences Among Logic Blocks. IEEE Trans. Very Large Scale Integr. Syst. 23(12): 3006-3014 (2015) - 2014
- [j200]Irith Pomeranz:
Reducing the input test data volume under transparent scan. IET Comput. Digit. Tech. 8(1): 1-10 (2014) - [j199]Irith Pomeranz:
Multi-cycle broadside tests with runs of constant primary input vectors. IET Comput. Digit. Tech. 8(2): 90-96 (2014) - [j198]Irith Pomeranz:
Sharing Logic for Built-In Generationof Functional Broadside Tests. IEEE Trans. Computers 63(4): 1048-1054 (2014) - [j197]Irith Pomeranz:
Unknown Output Values of Faulty Circuits and Output Response Compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(2): 323-327 (2014) - [j196]Irith Pomeranz:
Input Test Data Volume Reduction for Skewed-Load Tests by Additional Shifting of Scan-In States. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(4): 638-642 (2014) - [j195]Irith Pomeranz:
Selection of Functional Test Sequences With Overlaps. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(7): 1095-1099 (2014) - [j194]Irith Pomeranz:
Simultaneous Generation of Functional and Low-Power Non-Functional Broadside Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(8): 1245-1257 (2014) - [j193]Irith Pomeranz:
Functional Broadside Tests for Multistep Defect Diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(9): 1429-1433 (2014) - [j192]Irith Pomeranz:
Static Test Compaction for Scan Circuits by Using Restoration to Modify and Remove Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 1955-1964 (2014) - [j191]Irith Pomeranz:
Improving the Accuracy of Defect Diagnosis by Considering Fewer Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 2010-2014 (2014) - [j190]Irith Pomeranz:
Low-power skewed-load tests based on functional broadside tests. ACM Trans. Design Autom. Electr. Syst. 19(2): 18:1-18:18 (2014) - [j189]Irith Pomeranz:
Design-for-testability for multi-cycle broadside tests by holding of state variables. ACM Trans. Design Autom. Electr. Syst. 19(2): 19:1-19:20 (2014) - [j188]Irith Pomeranz:
Restoration-Based Procedures With Set Covering Heuristics for Static Test Compaction of Functional Test Sequences. IEEE Trans. Very Large Scale Integr. Syst. 22(4): 779-791 (2014) - [j187]Irith Pomeranz:
Test Compaction by Sharing of Transparent-Scan Sequences Among Logic Blocks. IEEE Trans. Very Large Scale Integr. Syst. 22(4): 792-802 (2014) - [j186]Irith Pomeranz:
Low-Power Test Generation by Merging of Functional Broadside Test Cubes. IEEE Trans. Very Large Scale Integr. Syst. 22(7): 1570-1582 (2014) - [j185]Irith Pomeranz:
Low-Power Diagnostic Test Sets for Transition Faults Based on Functional Broadside Tests. IEEE Trans. Very Large Scale Integr. Syst. 22(11): 2427-2431 (2014) - 2013
- [j184]Irith Pomeranz:
Static test compaction for mixed broadside and skewed-load transition fault test sets. IET Comput. Digit. Tech. 7(1): 21-28 (2013) - [j183]Irith Pomeranz:
On multi-cycle test cubes. IET Comput. Digit. Tech. 7(4): 182-189 (2013) - [j182]Irith Pomeranz:
Low-power test sets under test-related primary input constraints. Int. J. Crit. Comput. Based Syst. 4(3): 265-279 (2013) - [j181]Irith Pomeranz:
Diagnostic Test Sets with Increased Switching Activity for Transition Faults. J. Low Power Electron. 9(1): 133-140 (2013) - [j180]Irith Pomeranz:
An Adjacent Switching Activity Metric under Functional Broadside Tests. IEEE Trans. Computers 62(2): 404-410 (2013) - [j179]Irith Pomeranz:
Signal-Transition Patterns of Functional Broadside Tests. IEEE Trans. Computers 62(12): 2544-2549 (2013) - [j178]Irith Pomeranz:
Generation of Functional Broadside Tests for Logic Blocks With Constrained Primary Input Sequences. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(3): 442-452 (2013) - [j177]Irith Pomeranz:
Functional Broadside Tests With Incompletely Specified Scan-In States. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(9): 1445-1449 (2013) - [j176]Irith Pomeranz:
Non-Test Cubes for Test Generation Targeting Hard-to-Detect Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(12): 1957-1965 (2013) - [j175]Irith Pomeranz:
Built-in generation of multicycle functional broadside tests with observation points. ACM Trans. Design Autom. Electr. Syst. 19(1): 8:1-8:17 (2013) - [j174]Irith Pomeranz:
Built-In Generation of Functional Broadside Tests Using a Fixed Hardware Structure. IEEE Trans. Very Large Scale Integr. Syst. 21(1): 124-132 (2013) - [j173]Irith Pomeranz:
Computing Two-Pattern Test Cubes for Transition Path Delay Faults. IEEE Trans. Very Large Scale Integr. Syst. 21(3): 475-485 (2013) - [j172]Irith Pomeranz:
Broadside and Skewed-Load Tests Under Primary Input Constraints. IEEE Trans. Very Large Scale Integr. Syst. 21(4): 776-780 (2013) - [j171]Irith Pomeranz:
Reduced Power Transition Fault Test Sets for Circuits With Independent Scan Chain Modes. IEEE Trans. Very Large Scale Integr. Syst. 21(7): 1354-1359 (2013) - [j170]Irith Pomeranz:
Transition Fault Simulation Considering Broadside Tests as Partially-Functional Broadside Tests. IEEE Trans. Very Large Scale Integr. Syst. 21(7): 1359-1363 (2013) - [j169]Irith Pomeranz:
On Test Compaction of Broadside and Skewed-Load Test Cubes. IEEE Trans. Very Large Scale Integr. Syst. 21(9): 1705-1714 (2013) - [j168]Irith Pomeranz:
Functional Broadside Templates for Low-Power Test Generation. IEEE Trans. Very Large Scale Integr. Syst. 21(12): 2321-2325 (2013) - 2012
- [j167]Irith Pomeranz:
Test vector chains for increased resolution and reduced storage of diagnostic tests. IET Comput. Digit. Tech. 6(1): 12-18 (2012) - [j166]Irith Pomeranz:
Undetectable transition faults under broadside tests with constant primary input vectors. IET Comput. Digit. Tech. 6(2): 78-85 (2012) - [j165]Irith Pomeranz:
Functional broadside tests for embedded logic blocks. IET Comput. Digit. Tech. 6(4): 223-231 (2012) - [j164]Irith Pomeranz, Sudhakar M. Reddy:
Reset and partial-reset-based functional broadside tests. IET Comput. Digit. Tech. 6(4): 232-239 (2012) - [j163]Irith Pomeranz:
On the Computation of Common Test Data for Broadside and Skewed-Load Tests. IEEE Trans. Computers 61(4): 578-583 (2012) - [j162]Irith Pomeranz:
Concatenation of Functional Test Subsequences for Improved Fault Coverage and Reduced Test Length. IEEE Trans. Computers 61(6): 899-904 (2012) - [j161]Irith Pomeranz:
Fast Identification of Undetectable Transition Faults under Functional Broadside Tests. IEEE Trans. Computers 61(6): 905-910 (2012) - [j160]Irith Pomeranz:
On the Switching Activity and Static Test Compaction of Multicycle Scan-Based Tests. IEEE Trans. Computers 61(8): 1179-1188 (2012) - [j159]Irith Pomeranz:
Multipattern Scan-Based Test Sets With Small Numbers of Primary Input Sequences. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(2): 322-326 (2012) - [j158]Irith Pomeranz:
Multicycle Tests With Constant Primary Input Vectors for Increased Fault Coverage. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(9): 1428-1438 (2012) - [j157]Irith Pomeranz:
A Metric for Identifying Detectable Path Delay Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(11): 1734-1742 (2012) - [j156]Irith Pomeranz, Sudhakar M. Reddy:
Resolution of Diagnosis Based on Transition Faults. IEEE Trans. Very Large Scale Integr. Syst. 20(1): 172-176 (2012) - [j155]Irith Pomeranz:
Gradual Diagnostic Test Generation and Observation Point Insertion Based on the Structural Distance Between Indistinguished Fault Pairs. IEEE Trans. Very Large Scale Integr. Syst. 20(6): 1026-1035 (2012) - [j154]Irith Pomeranz:
Multi-Pattern $n$-Detection Stuck-At Test Sets for Delay Defect Coverage. IEEE Trans. Very Large Scale Integr. Syst. 20(6): 1156-1160 (2012) - [j153]Irith Pomeranz:
Generation of Mixed Test Sets for Transition Faults. IEEE Trans. Very Large Scale Integr. Syst. 20(10): 1895-1899 (2012) - [j152]Irith Pomeranz:
Non-Uniform Coverage by n -Detection Test Sets. IEEE Trans. Very Large Scale Integr. Syst. 20(11): 2138-2142 (2012) - 2011
- [j151]Irith Pomeranz, Sudhakar M. Reddy:
Primary input cones based on test sequences in synchronous sequential circuits. IET Comput. Digit. Tech. 5(1): 16-24 (2011) - [j150]Irith Pomeranz, Sudhakar M. Reddy:
Two-dimensional partially functional broadside tests. IET Comput. Digit. Tech. 5(4): 247-253 (2011) - [j149]Irith Pomeranz, Sudhakar M. Reddy:
Sizes of test sets for path delay faults using strong and weak non-robust tests. IET Comput. Digit. Tech. 5(5): 405-414 (2011) - [j148]Irith Pomeranz, Sudhakar M. Reddy:
Ranking of input cubes based on their lingering synchronisation effects and their use in random sequential test generation. IET Comput. Digit. Tech. 5(5): 415-423 (2011) - [j147]Irith Pomeranz, Sudhakar M. Reddy:
Transparent-Segmented-Scan without the Routing Overhead of Segmented-Scan. J. Low Power Electron. 7(2): 245-253 (2011) - [j146]Irith Pomeranz:
Generation of Multi-Cycle Broadside Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(8): 1253-1257 (2011) - [j145]Irith Pomeranz:
Scan Shift Power of Functional Broadside Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(9): 1416-1420 (2011) - [j144]Irith Pomeranz:
Subsets of Primary Input Vectors in Sequential Test Generation for Single Stuck-at Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(10): 1579-1583 (2011) - [j143]Irith Pomeranz, Sudhakar M. Reddy:
Reducing the switching activity of test sequences under transparent-scan. ACM Trans. Design Autom. Electr. Syst. 16(2): 17:1-17:21 (2011) - [j142]Irith Pomeranz, Sudhakar M. Reddy:
Fixed-State Tests for Delay Faults in Scan Designs. IEEE Trans. Very Large Scale Integr. Syst. 19(1): 142-146 (2011) - [j141]Irith Pomeranz, Sudhakar M. Reddy:
Input Necessary Assignments for Testing of Path Delay Faults in Standard-Scan Circuits. IEEE Trans. Very Large Scale Integr. Syst. 19(2): 333-337 (2011) - [j140]Irith Pomeranz, Sudhakar M. Reddy:
On Functional Broadside Tests With Functional Propagation Conditions. IEEE Trans. Very Large Scale Integr. Syst. 19(6): 1094-1098 (2011) - [j139]Irith Pomeranz, Sudhakar M. Reddy:
Broadside and Functional Broadside Tests for Partial-Scan Circuits. IEEE Trans. Very Large Scale Integr. Syst. 19(6): 1104-1108 (2011) - [j138]Irith Pomeranz, Sudhakar M. Reddy:
Static Test Data Volume Reduction Using Complementation or Modulo- M Addition. IEEE Trans. Very Large Scale Integr. Syst. 19(6): 1108-1112 (2011) - [j137]Irith Pomeranz, Sudhakar M. Reddy:
Reducing the Storage Requirements of a Test Sequence by Using One or Two Background Vectors. IEEE Trans. Very Large Scale Integr. Syst. 19(10): 1755-1764 (2011) - [j136]Irith Pomeranz, Sudhakar M. Reddy:
Test Strength: A Quality Metric for Transition Fault Tests in Full-Scan Circuits. IEEE Trans. Very Large Scale Integr. Syst. 19(10): 1907-1911 (2011) - 2010
- [j135]Irith Pomeranz, Sudhakar M. Reddy:
Diagnosis of path delay faults based on low-coverage tests. IET Comput. Digit. Tech. 4(2): 89-103 (2010) - [j134]Irith Pomeranz, Sudhakar M. Reddy:
Static test compaction for diagnostic test sets of full-scan circuits. IET Comput. Digit. Tech. 4(5): 365-373 (2010) - [j133]Irith Pomeranz, Sudhakar M. Reddy:
Test Sequences with Reduced and Increased Switching Activity. J. Low Power Electron. 6(2): 350-358 (2010) - [j132]Irith Pomeranz, Sudhakar M. Reddy:
Equivalence, Dominance, and Similarity Relations between Fault Pairs and a Fault Pair Collapsing Process for Fault Diagnosis. IEEE Trans. Computers 59(2): 150-158 (2010) - [j131]Irith Pomeranz, Sudhakar M. Reddy:
TOV: Sequential Test Generation by Ordering of Test Vectors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(3): 454-465 (2010) - [j130]Irith Pomeranz, Sudhakar M. Reddy:
On Test Generation With Test Vector Improvement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(3): 502-506 (2010) - [j129]Irith Pomeranz, Sudhakar M. Reddy:
On Clustering of Undetectable Single Stuck-At Faults and Test Quality in Full-Scan Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(7): 1135-1140 (2010) - [j128]Irith Pomeranz, Sudhakar M. Reddy:
Hazard-Based Detection Conditions for Improved Transition Path Delay Fault Coverage. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(9): 1449-1453 (2010) - [j127]Irith Pomeranz, Sudhakar M. Reddy:
On Undetectable Faults and Fault Diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11): 1832-1837 (2010) - [j126]Irith Pomeranz, Sudhakar M. Reddy:
Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Scan-Based Tests. IEEE Trans. Very Large Scale Integr. Syst. 18(2): 333-337 (2010) - [j125]Irith Pomeranz, Sudhakar M. Reddy:
Path Selection for Transition Path Delay Faults. IEEE Trans. Very Large Scale Integr. Syst. 18(3): 401-409 (2010) - [j124]Irith Pomeranz, Sudhakar M. Reddy:
Robust Fault Models Where Undetectable Faults Imply Logic Redundancy. IEEE Trans. Very Large Scale Integr. Syst. 18(8): 1230-1234 (2010) - [j123]Irith Pomeranz, Sudhakar M. Reddy:
Switching Activity as a Test Compaction Heuristic for Transition Faults. IEEE Trans. Very Large Scale Integr. Syst. 18(9): 1357-1361 (2010) - [j122]Irith Pomeranz, Sudhakar M. Reddy:
Selection of a Fault Model for Fault Diagnosis Based on Unique Responses. IEEE Trans. Very Large Scale Integr. Syst. 18(11): 1533-1543 (2010) - 2009
- [j121]Irith Pomeranz, Sudhakar M. Reddy:
Definition and generation of partially-functional broadside tests. IET Comput. Digit. Tech. 3(1): 1-13 (2009) - [j120]Irith Pomeranz, Sudhakar M. Reddy:
Same/different fault dictionary: an extended pass/fail fault dictionary with improved diagnostic resolution. IET Comput. Digit. Tech. 3(1): 85-93 (2009) - [j119]Irith Pomeranz, Sudhakar M. Reddy:
Test vector chains for increasing the fault coverage and numbers of detections. IET Comput. Digit. Tech. 3(2): 222-233 (2009) - [j118]Irith Pomeranz, Sudhakar M. Reddy:
Test compaction methods for transition faults under transparent-scan. IET Comput. Digit. Tech. 3(4): 315-328 (2009) - [j117]Irith Pomeranz, Sudhakar M. Reddy:
Functional Broadside Tests Under an Expanded Definition of Functional Operation Conditions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(1): 121-129 (2009) - [j116]Irith Pomeranz, Sudhakar M. Reddy:
Double-Single Stuck-at Faults: A Delay Fault Model for Synchronous Sequential Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(3): 426-432 (2009) - [j115]Irith Pomeranz, Sudhakar M. Reddy:
Forward-Looking Reverse Order Fault Simulation for n -Detection Test Sets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(9): 1424-1428 (2009) - [j114]Irith Pomeranz, Sudhakar M. Reddy:
Semiconcurrent Online Testing of Transition Faults through Output Response Comparison of Identical Circuits. IEEE Trans. Dependable Secur. Comput. 6(3): 231-240 (2009) - [j113]Irith Pomeranz, Sudhakar M. Reddy:
Using stuck-at tests to form scan-based tests for transition faults in standard-scan circuits. ACM Trans. Design Autom. Electr. Syst. 15(1): 7:1-7:22 (2009) - [j112]Irith Pomeranz, Sudhakar M. Reddy:
Random Test Generation With Input Cube Avoidance. IEEE Trans. Very Large Scale Integr. Syst. 17(1): 45-54 (2009) - 2008
- [j111]Irith Pomeranz, Sudhakar M. Reddy:
Functional Broadside Tests with Minimum and Maximum Switching Activity. J. Low Power Electron. 4(3): 429-437 (2008) - [j110]Irith Pomeranz, Sudhakar M. Reddy:
Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(1): 137-146 (2008) - [j109]Irith Pomeranz, Sudhakar M. Reddy:
Primary Input Vectors to Avoid in Random Test Sequences for Synchronous Sequential Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(1): 193-197 (2008) - [j108]Irith Pomeranz, Sudhakar M. Reddy:
Scan-Based Delay Test Types and Their Effect on Power Dissipation During Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(2): 398-403 (2008) - [j107]Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy:
On Complete Functional Broadside Tests for Transition Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(3): 583-587 (2008) - [j106]Irith Pomeranz, Sudhakar M. Reddy:
On the Saturation of n-Detection Test Generation by Different Definitions With Increased n. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(5): 946-957 (2008) - [j105]Irith Pomeranz, Sudhakar M. Reddy:
Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects. IEEE Trans. Very Large Scale Integr. Syst. 16(1): 98-107 (2008) - [j104]Irith Pomeranz, Sudhakar M. Reddy:
Improving the Transition Fault Coverage of Functional Broadside Tests by Observation Point Insertion. IEEE Trans. Very Large Scale Integr. Syst. 16(7): 931-936 (2008) - 2007
- [j103]Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski:
Scan-Based Tests with Low Switching Activity. IEEE Des. Test Comput. 24(3): 268-275 (2007) - [j102]Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Bashir M. Al-Hashimi:
Enhancing delay fault coverage through low-power segmented scan. IET Comput. Digit. Tech. 1(3): 220-229 (2007) - [j101]Irith Pomeranz, Sudhakar M. Reddy:
Worst-case and average-case analysis of n-detection test sets and test generation strategies. IET Comput. Digit. Tech. 1(4): 353-363 (2007) - [j100]Irith Pomeranz, Sudhakar M. Reddy:
Effectiveness of scan-based delay fault tests in diagnosis of transition faults. IET Comput. Digit. Tech. 1(5): 537-545 (2007) - [j99]Irith Pomeranz:
Invariant States and Redundant Logic in Synchronous Sequential Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(6): 1171-1175 (2007) - [j98]Irith Pomeranz, Sudhakar M. Reddy:
Generation of Broadside Transition-Fault Test Sets That Detect Four-Way Bridging Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7): 1311-1319 (2007) - [j97]Irith Pomeranz, Sudhakar M. Reddy, Srikanth Venkataraman:
z-Diagnosis: A Framework for Diagnostic Fault Simulation and Test Generation Utilizing Subsets of Outputs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9): 1700-1712 (2007) - [j96]Irith Pomeranz, Sudhakar M. Reddy:
Forming N-detection test sets without test generation. ACM Trans. Design Autom. Electr. Syst. 12(2): 18 (2007) - 2006
- [j95]Yoshinobu Higami, Seiji Kajihara, Irith Pomeranz, Shin-ya Kobayashi, Yuzo Takamatsu:
On Finding Don't Cares in Test Sequences for Sequential Circuits. IEICE Trans. Inf. Syst. 89-D(11): 2748-2755 (2006) - [j94]Irith Pomeranz, Sudhakar M. Reddy:
On Generating Tests that Avoid the Detection of Redundant Faults in Synchronous Sequential Circuits with Full Scan. IEEE Trans. Computers 55(4): 491-495 (2006) - [j93]Irith Pomeranz, Sudhakar M. Reddy:
Scan-BIST based on transition probabilities for circuits with single and multiple scan chains. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(3): 591-596 (2006) - [j92]Irith Pomeranz, Sudhakar M. Reddy:
Transparent DFT: a design for testability and test generation approach for synchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 1170-1175 (2006) - [j91]Irith Pomeranz, Sudhakar M. Reddy:
Generation of Functional Broadside Tests for Transition Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 2207-2218 (2006) - [j90]Irith Pomeranz, Sudhakar M. Reddy:
Using Dummy Bridging Faults to Define Reduced Sets of Target Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 2219-2227 (2006) - [j89]Irith Pomeranz, Sudhakar M. Reddy:
Improved n-Detection Test Sequences Under Transparent Scan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11): 2492-2501 (2006) - 2005
- [j88]Irith Pomeranz, Sudhakar M. Reddy:
On masking of redundant faults in synchronous sequential circuits with design-for-testability logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(2): 288-294 (2005) - [j87]Irith Pomeranz, Sudhakar M. Reddy:
On fault equivalence, fault dominance, and incompletely specified test sets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(8): 1271-1274 (2005) - [j86]Yonsang Cho, Irith Pomeranz, Sudhakar M. Reddy:
On reducing test application time for scan circuits using limited scan operations and transfer sequences. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(10): 1594-1605 (2005) - [j85]Irith Pomeranz, Sudhakar M. Reddy:
Concurrent Online Testing of Identical Circuits Using Nonidentical Input Vectors. IEEE Trans. Dependable Secur. Comput. 2(3): 190-200 (2005) - [j84]Irith Pomeranz, Sudhakar M. Reddy:
Autoscan: a scan design without external scan inputs or outputs. IEEE Trans. Very Large Scale Integr. Syst. 13(9): 1087-1095 (2005) - 2004
- [j83]Seiji Kajihara, Kenjiro Taniguchi, Kohei Miyase, Irith Pomeranz, Sudhakar M. Reddy:
Don't Care Identification and Statistical Encoding for Test Data Compression. IEICE Trans. Inf. Syst. 87-D(3): 544-550 (2004) - [j82]Irith Pomeranz, Sandip Kundu, Sudhakar M. Reddy:
Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units. IEEE Trans. Computers 53(1): 83-88 (2004) - [j81]Irith Pomeranz, Sudhakar M. Reddy:
On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit. IEEE Trans. Computers 53(9): 1121-1133 (2004) - [j80]Irith Pomeranz, Sudhakar M. Reddy:
A Measure of Quality for n-Detection Test Sets. IEEE Trans. Computers 53(11): 1497-1503 (2004) - [j79]Irith Pomeranz, Sudhakar M. Reddy:
Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Nonscan Input Sequences and a Lower Bound on the Number of Tests. IEEE Trans. Computers 53(12): 1569-1581 (2004) - [j78]Irith Pomeranz:
Constrained test generation for embedded synchronous sequential circuits with serial-input access. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1): 164-172 (2004) - [j77]Irith Pomeranz:
Reducing test-data volume using P-testable scan chains in circuits with multiple scan chains. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(10): 1465-1478 (2004) - [j76]Irith Pomeranz, Sudhakar M. Reddy:
Vector-restoration-based static compaction using random initial omission. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(11): 1587-1592 (2004) - [j75]Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu:
On the characterization and efficient computation of hard-to-detect bridging faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(12): 1640-1649 (2004) - [j74]Irith Pomeranz, Sudhakar M. Reddy:
Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations. IEEE Trans. Very Large Scale Integr. Syst. 12(7): 780-788 (2004) - [j73]Irith Pomeranz, Yervant Zorian:
Fault isolation for nonisolated blocks. IEEE Trans. Very Large Scale Integr. Syst. 12(12): 1385-1388 (2004) - 2003
- [j72]Yun Shao, Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara:
On Selecting Testable Paths in Scan Designs. J. Electron. Test. 19(4): 447-456 (2003) - [j71]Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz:
A Low Power Pseudo-Random BIST Technique. J. Electron. Test. 19(6): 637-644 (2003) - [j70]Mohamed A. Gomaa, Chad Scarbrough, T. N. Vijaykumar, Irith Pomeranz:
Transient-Fault Recovery for Chip Multiprocessors. IEEE Micro 23(6): 76-83 (2003) - [j69]Irith Pomeranz, Sudhakar M. Reddy:
Test enrichment for path delay faults using multiple sets of target faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(1): 82-90 (2003) - [j68]Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz:
Reverse-order-restoration-based static test compaction for synchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(3): 293-304 (2003) - [j67]M. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana:
Fault equivalence identification in combinational circuits using implication and evaluation techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(7): 922-936 (2003) - [j66]Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz:
PROPTEST: a property-based test generator for synchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(8): 1080-1091 (2003) - [j65]Irith Pomeranz, Sudhakar M. Reddy:
Theorems for identifying undetectable faults in partial-scan circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(8): 1092-1097 (2003) - [j64]Irith Pomeranz, Sudhakar M. Reddy:
Test data compression based on input-output dependence. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(10): 1450-1455 (2003) - [j63]Irith Pomeranz, Sudhakar M. Reddy:
Transparent scan: a new approach to test generation and test compaction for scan circuits that incorporates limited scan operations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(12): 1663-1670 (2003) - [j62]Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz:
On test data volume reduction for multiple scan chain designs. ACM Trans. Design Autom. Electr. Syst. 8(4): 460-469 (2003) - 2002
- [j61]Irith Pomeranz, Sudhakar M. Reddy:
Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Input Sequences Using Single and Multiple Fault Detection Times. IEEE Trans. Computers 51(4): 409-419 (2002) - [j60]Irith Pomeranz, Sudhakar M. Reddy:
Enumeration of Test Sequences in Increasing Chronological Order to Improve the Levels of Compaction Achieved by Vector Omission. IEEE Trans. Computers 51(7): 866-872 (2002) - [j59]Irith Pomeranz, Sudhakar M. Reddy:
A Storage-Based Built-In Test Pattern Generation Method for Scan Circuits Based on Partitioning and Reduction of a Precomputed Test Set. IEEE Trans. Computers 51(11): 1282-1293 (2002) - [j58]Irith Pomeranz, Sudhakar M. Reddy:
Property-based test generation for scan designs and the effects ofthe test application scheme and scan selection on the number ofdetectable faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(5): 628-637 (2002) - [j57]Irith Pomeranz, Sudhakar M. Reddy:
Test compaction for at-speed testing of scan circuits based onnonscan test. sequences and removal of transfer sequences. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(6): 706-714 (2002) - [j56]Irith Pomeranz, Sudhakar M. Reddy:
n-pass n-detection fault simulation and its applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(8): 980-986 (2002) - [j55]Irith Pomeranz:
On the use of random limited-scan to improve at-speed randompattern testing of scan circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(9): 1068-1076 (2002) - 2001
- [j54]Irith Pomeranz, Sudhakar M. Reddy:
Design-for-testability to achieve complete coverage of delay faults in standard full scan circuits. J. Syst. Archit. 47(3-4): 357-373 (2001) - [j53]Irith Pomeranz, Sudhakar M. Reddy:
Vector replacement to improve static-test compaction forsynchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(2): 336-342 (2001) - [j52]Irith Pomeranz, Sudhakar M. Reddy:
On diagnosis and diagnostic test generation for pattern-dependenttransition faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(6): 791-800 (2001) - [j51]Irith Pomeranz, Y. Zonan:
Testing of scan circuits containing nonisolated random-logic legacycores. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(8): 980-993 (2001) - [j50]Irith Pomeranz, Sudhakar M. Reddy:
Forward-looking fault simulation for improved static compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(10): 1262-1265 (2001) - [j49]Irith Pomeranz, Sudhakar M. Reddy:
A built-in self-test method for diagnosis of synchronous sequential circuits. IEEE Trans. Very Large Scale Integr. Syst. 9(2): 290-296 (2001) - [j48]Irith Pomeranz, Sudhakar M. Reddy:
Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units. IEEE Trans. Very Large Scale Integr. Syst. 9(5): 679-689 (2001) - 2000
- [j47]Irith Pomeranz, Sudhakar M. Reddy:
Static Test Compaction for Scan-Based Designs to Reduce Test Application Time. J. Electron. Test. 16(5): 541-552 (2000) - [j46]Irith Pomeranz, Sudhakar M. Reddy:
On Finding a Minimal Functional Description of a Finite-State Machine for Test Generation for Adjacent Machines. IEEE Trans. Computers 49(1): 88-94 (2000) - [j45]Irith Pomeranz, Sudhakar M. Reddy:
On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits. IEEE Trans. Computers 49(2): 175-181 (2000) - [j44]Irith Pomeranz, Sudhakar M. Reddy:
Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits. IEEE Trans. Computers 49(6): 596-607 (2000) - [j43]Irith Pomeranz, Sudhakar M. Reddy:
On n-detection test sets and variable n-detection test sets fortransition faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(3): 372-383 (2000) - [j42]Irith Pomeranz, Sudhakar M. Reddy:
A diagnostic test generation procedure based on test elimination byvector omission for synchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(5): 589-600 (2000) - [j41]Irith Pomeranz, Sudhakar M. Reddy:
On synchronizable circuits and their synchronizing sequences. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(9): 1086-1092 (2000) - 1999
- [j40]Irith Pomeranz, Sudhakar M. Reddy:
A Cone-Based Genetic Optimization Procedure for Test Generation and Its Application to n-Detections in Combinational Circuits. IEEE Trans. Computers 48(10): 1145-1152 (1999) - [j39]Irith Pomeranz, Sudhakar M. Reddy:
A comment on "Improving a nonenumerative method to estimate path delay fault coverage". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(5): 665-666 (1999) - [j38]Irith Pomeranz, Sudhakar M. Reddy, Ruifeng Guo:
Static test compaction for synchronous sequential circuits based on vector restoration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(7): 1040-1049 (1999) - 1998
- [j37]Irith Pomeranz, Sudhakar M. Reddy:
Delay fault models for VLSI circuits1. Integr. 26(1-2): 21-40 (1998) - [j36]Irith Pomeranz, Sudhakar M. Reddy:
Location of Stuck-At Faults and Bridging Faults Based on Circuit Partitioning. IEEE Trans. Computers 47(10): 1124-1135 (1998) - [j35]Irith Pomeranz, Sudhakar M. Reddy:
Low-complexity fault simulation under the multiple observation time and the restricted multiple observation time testing approaches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(3): 269-278 (1998) - [j34]Irith Pomeranz, Sudhakar M. Reddy:
Design-for-testability for path delay faults in large combinational circuits using test points. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(4): 333-343 (1998) - [j33]Irith Pomeranz, Sudhakar M. Reddy:
Test sequences to achieve high defect coverage for synchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(10): 1017-1029 (1998) - [j32]Vinay Dabholkar, Sreejit Chakravarty, Irith Pomeranz, Sudhakar M. Reddy:
Techniques for minimizing power dissipation in scan and combinational circuits during test application. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(12): 1325-1333 (1998) - [j31]Irith Pomeranz, Sudhakar M. Reddy:
Functional test generation for delay faults in combinational circuits. ACM Trans. Design Autom. Electr. Syst. 3(2): 231-248 (1998) - [j30]Irith Pomeranz, Sudhakar M. Reddy:
On methods to match a test pattern generator to a circuit-under-test. IEEE Trans. Very Large Scale Integr. Syst. 6(3): 432-444 (1998) - 1997
- [j29]Irith Pomeranz, Sudhakar M. Reddy:
On Dictionary-Based Fault Location in Digital Logic Circuits. IEEE Trans. Computers 46(1): 48-59 (1997) - [j28]Irith Pomeranz, Sudhakar M. Reddy:
Test Generation for Multiple State-Table Faults in Finite-State Machines. IEEE Trans. Computers 46(7): 783-794 (1997) - [j27]Irith Pomeranz, Sudhakar M. Reddy:
LOCSTEP: a logic-simulation-based test generation procedure. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(5): 544-554 (1997) - [j26]Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara:
Compact test sets for high defect coverage. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(8): 923-930 (1997) - [j25]Irith Pomeranz, Sudhakar M. Reddy:
On error correction in macro-based circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(10): 1088-1100 (1997) - 1996
- [j24]Irith Pomeranz, Sudhakar M. Reddy:
On Removing Redundancies from Synchronous Sequential Circuits with Synchronizing Sequences. IEEE Trans. Computers 45(1): 20-32 (1996) - [j23]Irith Pomeranz, Sudhakar M. Reddy:
On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits. IEEE Trans. Computers 45(1): 50-62 (1996) - 1995
- [j22]Tatiana Orenstein, Zvi Kohavi, Irith Pomeranz:
An optimal algorithm for cycle breaking in directed graphs. J. Electron. Test. 7(1-2): 71-81 (1995) - [j21]Irith Pomeranz, Sudhakar M. Reddy:
Aliasing Computation Using Fault Simulation with Fault Dropping. IEEE Trans. Computers 44(1): 139-144 (1995) - [j20]Irith Pomeranz, Sudhakar M. Reddy:
On Fault Simulation for Synchronous Sequential Circuits. IEEE Trans. Computers 44(2): 335-340 (1995) - [j19]Irith Pomeranz, Sudhakar M. Reddy:
INCREDYBLE: A New Search Strategy for Design Automation Problems with Applications to Testing. IEEE Trans. Computers 44(6): 792-804 (1995) - [j18]Irith Pomeranz, Sudhakar M. Reddy:
On correction of multiple design errors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(2): 255-264 (1995) - [j17]Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy:
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12): 1496-1504 (1995) - [j16]Irith Pomeranz, Sudhakar M. Reddy, Prasanti Uppaluri:
NEST: a nonenumerative test generation method for path delay faults in combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12): 1505-1515 (1995) - 1994
- [j15]Irith Pomeranz, Sudhakar M. Reddy:
Application of Homing Sequences to Synchronous Sequential Circuit Testing. IEEE Trans. Computers 43(5): 569-580 (1994) - [j14]Irith Pomeranz, Sudhakar M. Reddy:
On the Role of Hardware Reset in Synchronous Sequential Circuit Test Generation. IEEE Trans. Computers 43(9): 1100-1105 (1994) - [j13]Irith Pomeranz, Sudhakar M. Reddy:
An efficient nonenumerative method to estimate the path delay fault coverage in combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(2): 240-250 (1994) - [j12]Irith Pomeranz, Sudhakar M. Reddy:
SPADES-ACE: a simulator for path delay faults in sequential circuits with extensions to arbitrary clocking schemes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(2): 251-263 (1994) - [j11]Irith Pomeranz, Sudhakar M. Reddy:
On achieving complete fault coverage for sequential machines. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(3): 378-386 (1994) - [j10]Irith Pomeranz, Sudhakar M. Reddy:
On determining symmetries in inputs of logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(11): 1428-1434 (1994) - 1993
- [j9]Irith Pomeranz, Sudhakar M. Reddy:
Classification of Faults in Synchronous Sequential Circuits. IEEE Trans. Computers 42(9): 1066-1077 (1993) - [j8]Irith Pomeranz, Sudhakar M. Reddy:
Testing of Fault-Tolerant Hardware Through Partial Control of Inputs. IEEE Trans. Computers 42(10): 1267-1271 (1993) - [j7]Irith Pomeranz, Lakshmi N. Reddy, Sudhakar M. Reddy:
COMPACTEST: a method to generate compact test sets for combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(7): 1040-1049 (1993) - [j6]Irith Pomeranz, Sudhakar M. Reddy:
3-weight pseudo-random test generation based on a deterministic test set for combinational and sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(7): 1050-1058 (1993) - [j5]Irith Pomeranz, Kwang-Ting Cheng:
STOIC: state assignment based on output/input functions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(8): 1123-1131 (1993) - 1992
- [j4]Irith Pomeranz, Sudhakar M. Reddy:
The Multiple Observation Time Test Strategy. IEEE Trans. Computers 41(5): 627-637 (1992) - [j3]Irith Pomeranz, Zvi Kohavi:
A limited exponential complexity algorithm for increasing the testability of digital circuits by testing-module insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(2): 247-259 (1992) - 1991
- [j2]Irith Pomeranz, Zvi Kohavi:
The minimum test set problem for circuits with nonreconvergent fanout. J. Electron. Test. 2(4): 339-349 (1991) - [j1]Irith Pomeranz, Zvi Kohavi:
Polynomial Complexity Algorithms for Increasing the Testability of Digital Circuits by Testing Module Insertion. IEEE Trans. Computers 40(11): 1198-1214 (1991)
Conference and Workshop Papers
- 2023
- [c411]Irith Pomeranz:
Compaction of Functional Broadside Tests for Path Delay Faults Using Clusters of Propagation Lines. ITC 2023: 105-110 - [c410]Subashini Gopalsamy, Irith Pomeranz:
Fully Deterministic Storage Based Logic Built-In Self-Test. VTS 2023: 1-7 - [c409]Irith Pomeranz:
Expanding a Pool of Functional Test Sequences to Support Test Compaction. VTS 2023: 1-7 - [c408]Irith Pomeranz:
Compact Set of Functional Broadside Tests with Fault Detection on Primary Outputs. VTS 2023: 1-7 - 2022
- [c407]Irith Pomeranz:
Two-Dimensional Test Generation Objective. ATS 2022: 108-113 - [c406]Irith Pomeranz:
Selecting Path Delay Faults Through the Largest Subcircuits of Uncovered Lines. ATS 2022: 114-119 - [c405]Hari Addepalli, Irith Pomeranz, M. Enamul Amyeen, Suriyaprakash Natarajan, Arani Sinha, Srikanth Venkataraman:
Using Fault Detection Tests to Produce Diagnostic Tests Targeting Large Sets of Candidate Faults. ATS 2022: 120-125 - [c404]Irith Pomeranz:
Usable Circuits with Imperfect Scan Logic. ATS 2022: 156-161 - [c403]Irith Pomeranz:
Storage-Based Logic Built-In Self-Test with Variable-Length Test Data. DFT 2022: 1-6 - [c402]Irith Pomeranz:
Compaction of Compressed Bounded Transparent-Scan Test Sets. ACM Great Lakes Symposium on VLSI 2022: 339-343 - [c401]Hari Addepalli, Irith Pomeranz:
Algorithms for the Selection of Applied Tests when a Stored Test Produces Many Applied Tests. ACM Great Lakes Symposium on VLSI 2022: 345-349 - [c400]Jerin Joe, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski:
Test Generation for an Iterative Design Flow with RTL Changes. ITC 2022: 305-313 - [c399]Irith Pomeranz:
Transforming an $n$-Detection Test Set into a Test Set for a Variety of Fault Models. ITC 2022: 474-478 - [c398]Jerin Joe, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski:
Fast Test Generation for Structurally Similar Circuits. VTS 2022: 1-7 - 2021
- [c397]Irith Pomeranz:
Positive and Negative Extra Clocking of LFSR Seeds for Reduced Numbers of Stored Tests. ATS 2021: 109-114 - [c396]Irith Pomeranz:
Zoom-In Feature for Storage-Based Logic Built-In Self-Test. DFT 2021: 1-6 - [c395]Irith Pomeranz:
Compact Set of LFSR Seeds for Diagnostic Tests. VTS 2021: 1-7 - 2020
- [c394]Irith Pomeranz:
Improving a Test Set to Cover Test Holes by Detecting Gate-Exhaustive Faults. DFT 2020: 1-4 - [c393]Irith Pomeranz:
Storage Based Built-In Test Pattern Generation Method for Close-to-Functional Broadside Tests. IOLTS 2020: 1-4 - [c392]Irith Pomeranz, Sandip Kundu:
Reduced Fault Coverage as a Target for Design Scaffolding Security. IOLTS 2020: 1-6 - [c391]Irith Pomeranz:
Selecting Close-to-Functional Path Delay Faults for Test Generation. ITC 2020: 1-5 - [c390]Irith Pomeranz:
Input Test Data Volume Reduction Using Seed Complementation and Multiple LFSRs. VTS 2020: 1-6 - [c389]Irith Pomeranz:
Non-Masking Non-Robust Tests for Path Delay Faults. VTS 2020: 1-6 - 2019
- [c388]Naixing Wang, Chen Wang, Kun-Han Tsai, Wu-Tung Cheng, Xijiang Lin, Mark Kassab, Irith Pomeranz:
TEA: A Test Generation Algorithm for Designs with Timing Exceptions. ATS 2019: 19-24 - [c387]Naixing Wang, Irith Pomeranz, Sudhakar M. Reddy, Arani Sinha, Srikanth Venkataraman:
Resynthesis for Avoiding Undetectable Faults Based on Design-for-Manufacturability Guidelines. DATE 2019: 1022-1027 - [c386]Irith Pomeranz:
Iterative Test Generation for Gate-Exhaustive Faults to Cover the Sites of Undetectable Target Faults. ITC 2019: 1-7 - [c385]Irith Pomeranz:
Compaction of a Functional Broadside Test Set through the Compaction of a Functional Test Sequence without Sequential Fault Simulation. ITC 2019: 1-7 - [c384]Irith Pomeranz:
Test Compaction Under Bounded Transparent-Scan. VTS 2019: 1-6 - [c383]Irith Pomeranz, Vivek Chickermane, Srikanth Venkataraman:
Observation Point Placement for Improved Logic Diagnosis based on Large Sets of Candidate Faults. VTS 2019: 1-6 - 2018
- [c382]Irith Pomeranz:
Postprocessing Procedure for Reducing the Faulty Switching Activity of a Low-Power Test Set. DFT 2018: 1-6 - [c381]Naixing Wang, Irith Pomeranz, Brady Benware, M. Enamul Amyeen, Srikanth Venkataraman:
Improving the Resolution of Multiple Defect Diagnosis by Removing and Selecting Tests. DFT 2018: 1-6 - [c380]Irith Pomeranz:
Covering undetected transition fault sites with optimistic unspecified transition faults under multicycle tests. ETS 2018: 1-2 - [c379]Irith Pomeranz, Srikanth Venkataraman:
Interconnect-aware tests to complement gate-exhaustive tests. ETS 2018: 1-6 - [c378]Irith Pomeranz:
On Close-to-Functional Test Sequences. ITC 2018: 1-8 - 2017
- [c377]Irith Pomeranz:
Test Compaction with Dynamic Updating of Faults for Coverage of Undetected Transition Fault Sites. ATS 2017: 34-39 - [c376]Irith Pomeranz:
Compaction of a Transparent-Scan Sequence to Reduce the Fail Data Volume for Scan Chain Faults. ATS 2017: 133-138 - [c375]Irith Pomeranz:
A bridging fault model for line coverage in the presence of undetected transition faults. DATE 2017: 938-941 - [c374]Naixing Wang, Bo Yao, Xijiang Lin, Irith Pomeranz:
Functional Broadside Test Generation Using a Commercial ATPG Tool. ISVLSI 2017: 308-313 - [c373]Irith Pomeranz:
Static Compaction by Merging of Seeds for LFSR-Based Test Generation. ISVLSI 2017: 314-319 - [c372]Irith Pomeranz:
Selecting target bridging faults for uniform circuit coverage. ITC 2017: 1-7 - [c371]Irith Pomeranz:
POSTT: Path-oriented static test compaction for transition faults in scan circuits. ITC 2017: 1-8 - [c370]Srikanth Venkataraman, Irith Pomeranz, Shraddha Bodhe, M. Enamul Amyeen:
Test reordering for improved scan chain diagnosis using an enhanced defect diagnosis procedure. ITC 2017: 1-9 - [c369]Irith Pomeranz:
Fail data reduction for diagnosis of scan chain faults under transparent-scan. VTS 2017: 1-6 - [c368]Irith Pomeranz:
Using piecewise-functional broadside tests for functional broadside test compaction. VTS 2017: 1-6 - 2016
- [c367]Irith Pomeranz, Sudhakar M. Reddy:
On the Switching Activity in Faulty Circuits During Test Application. ATS 2016: 13-18 - [c366]M. Enamul Amyeen, Irith Pomeranz, Srikanth Venkataraman:
A Joint Diagnostic Test Generation Procedure with Dynamic Test Compaction. ATS 2016: 138-143 - [c365]Irith Pomeranz:
A Compact Set of Seeds for LFSR-Based Test Generation from a Fully-Specified Compact Test Set. ISVLSI 2016: 361-366 - [c364]Shraddha Bodhe, M. Enamul Amyeen, Clariza Galendez, Houston Mooers, Irith Pomeranz, Srikanth Venkataraman:
Reduction of diagnostic fail data volume and tester time using a dynamic N-cover algorithm. VTS 2016: 1-6 - [c363]Irith Pomeranz:
A convergent procedure for partially-reachable states. VTS 2016: 1-6 - 2015
- [c362]Irith Pomeranz:
Generation of close-to-functional broadside tests with equal primary input vectors. DAC 2015: 137:1-137:6 - [c361]Irith Pomeranz:
Piecewise-functional broadside tests based on intersections of reachable states. DFTS 2015: 133-138 - [c360]Marco Gaudesi, Matteo Sonza Reorda, Irith Pomeranz:
On test program compaction. ETS 2015: 1-6 - [c359]Nitin, Irith Pomeranz, T. N. Vijaykumar:
FaultHound: value-locality-based soft-fault tolerance. ISCA 2015: 668-681 - [c358]Irith Pomeranz:
Reducing the Storage Requirements of a Set of Functional Test Sequences by Using a Background Sequence. ISVLSI 2015: 155-160 - [c357]Irith Pomeranz:
Improving the accuracy of defect diagnosis by considering reduced diagnostic information. VTS 2015: 1-6 - [c356]Irith Pomeranz:
Test vector omission with minimal sets of simulated faults. VTS 2015: 1-6 - [c355]Irith Pomeranz:
Test compaction by test cube merging for four-way bridging faults. VTS 2015: 1-6 - [c354]Irith Pomeranz:
A definition of the number of detections for faults with single tests in a compact scan-based test set. VTS 2015: 1-6 - 2014
- [c353]Irith Pomeranz:
Test and non-test cubes for diagnostic test generation based on merging of test cubes. DATE 2014: 1-4 - [c352]Irith Pomeranz:
Substituting transition faults with path delay faults as a basic delay fault model. DATE 2014: 1-6 - [c351]Irith Pomeranz:
A distance-based test cube merging procedure for compatible and incompatible test cubes. ETS 2014: 1-2 - [c350]Bo Yao, Irith Pomeranz, Srikanth Venkataraman, M. Enamul Amyeen:
Built-in generation of functional broadside tests considering primary input constraints. ACM Great Lakes Symposium on VLSI 2014: 237-238 - [c349]Irith Pomeranz:
FDPIC: Generation of Functional Test Sequences Based on Fault-Dependent Primary Input Cubes. ISVLSI 2014: 308-313 - [c348]Irith Pomeranz:
OBO: An Output-by-Output Scoring Algorithm for Fault Diagnosis. ISVLSI 2014: 314-319 - [c347]Rohit Kapur, Irith Pomeranz:
Innovative practices session 10C: Advances in DFT and compression. VTS 2014: 1 - [c346]Irith Pomeranz:
Fault simulation with test switching for static test compaction. VTS 2014: 1-6 - [c345]Irith Pomeranz:
On the use of multi-cycle tests for storage of two-cycle broadside tests. VTS 2014: 1-6 - 2013
- [c344]Irith Pomeranz:
On candidate fault sets for fault diagnosis and dominance graphs of equivalence classes. DATE 2013: 1083-1088 - [c343]Irith Pomeranz:
Classes of difficult-to-diagnose transition fault clusters. DFTS 2013: 1-6 - [c342]Irith Pomeranz:
Generation of compact multi-cycle diagnostic test sets. ETS 2013: 1 - [c341]Bo Yao, Arani Sinha, Irith Pomeranz:
Path selection based on static timing analysis considering input necessary assignments. VTS 2013: 1-6 - 2012
- [c340]Irith Pomeranz:
Generation and compaction of mixed broadside and skewed-load n-detection test sets for transition faults. DFT 2012: 37-42 - [c339]Irith Pomeranz:
Built-in generation of multi-cycle broadside tests. DFT 2012: 146-151 - [c338]Irith Pomeranz:
Maintaining proximity to functional operation conditions under enhanced-scan tests based on functional broadside tests. DFT 2012: 239-244 - [c337]Irith Pomeranz:
On the detection of path delay faults by functional broadside tests. ETS 2012: 1-6 - [c336]Amit Kumar, Sudhakar M. Reddy, Bernd Becker, Irith Pomeranz:
Performance aware partitioning for 3D-SOCs. ISOCC 2012: 163-166 - [c335]Amit Kumar, Sudhakar M. Reddy, Irith Pomeranz, Bernd Becker:
TSV and DFT cost aware circuit partitioning for 3D-SOCs. ISQED 2012: 21-26 - [c334]Irith Pomeranz:
Static test compaction for transition faults under the hazard-based detection conditions. VTS 2012: 176-181 - 2011
- [c333]J. M. Howard, Sudhakar M. Reddy, Irith Pomeranz, Bernd Becker:
Fault diagnosis aware ATE assisted test response compaction. ASP-DAC 2011: 812-817 - [c332]Irith Pomeranz:
Diagnosis of transition fault clusters. DAC 2011: 429-434 - [c331]Irith Pomeranz:
Built-in generation of functional broadside tests. DATE 2011: 1297-1302 - [c330]Amit Kumar, Sudhakar M. Reddy, Irith Pomeranz, Bernd Becker:
Hyper-graph based partitioning to reduce DFT cost for pre-bond 3D-IC testing. DATE 2011: 1424-1429 - [c329]Xiaoxin Fan, Sudhakar M. Reddy, Irith Pomeranz:
Max-Fill: A method to generate high quality delay tests. DDECS 2011: 375-380 - [c328]Irith Pomeranz:
On Transition Fault Diagnosis Using Multicycle At-Speed Broadside Tests. ETS 2011: 189-194 - [c327]Irith Pomeranz:
Augmenting Functional Broadside Tests for Transition Fault Coverage with Bounded Switching Activity. PRDC 2011: 38-44 - [c326]Irith Pomeranz:
Generation of Mixed Broadside and Skewed-Load Diagnostic Test Sets for Transition Faults. PRDC 2011: 45-52 - [c325]Irith Pomeranz:
Static test compaction for delay fault test sets consisting of broadside and skewed-load tests. VTS 2011: 84-89 - [c324]Irith Pomeranz:
On clustering of undetectable transition faults in standard-scan circuits. VTS 2011: 128-133 - 2010
- [c323]Irith Pomeranz, Sudhakar M. Reddy:
Functional and partially-functional skewed-load tests. ASP-DAC 2010: 505-510 - [c322]Irith Pomeranz, Sudhakar M. Reddy:
On Bias in Transition Coverage of Test Sets for Path Delay Faults. Asian Test Symposium 2010: 349-352 - [c321]Irith Pomeranz, Sudhakar M. Reddy:
Reducing the storage requirements of a test sequence by using a background vector. DATE 2010: 1237-1242 - [c320]Irith Pomeranz, Sudhakar M. Reddy:
On reset based functional broadside tests. DATE 2010: 1438-1443 - [c319]Irith Pomeranz, Sudhakar M. Reddy:
Gradual Diagnostic Test Generation Based on the Structural Distance between Indistinguished Fault Pairs. DFT 2010: 349-357 - [c318]Irith Pomeranz, Sudhakar M. Reddy:
Input test data volume reduction based on test vector chains. ETS 2010: 240 - [c317]Bo Yao, Irith Pomeranz, Sudhakar M. Reddy:
Deterministic broadside test generation for transition path delay faults. ACM Great Lakes Symposium on VLSI 2010: 135-138 - [c316]Irith Pomeranz, Sudhakar M. Reddy:
Selecting state variables for improved on-line testability through output response comparison of identical circuits. IOLTS 2010: 179-184 - [c315]Narendra Devta-Prasanna, Arun Gunda, Sudhakar M. Reddy, Irith Pomeranz:
Multiple fault activation cycle tests for transistor stuck-open faults. ITC 2010: 821 - [c314]Irith Pomeranz, Sudhakar M. Reddy:
Output-Dependent Diagnostic Test Generation. VLSI Design 2010: 3-8 - [c313]Irith Pomeranz, Sudhakar M. Reddy:
Identifying Tests for Logic Fault Models Involving Subsets of Lines without Fault Enumeration. VLSI Design 2010: 39-44 - [c312]Irith Pomeranz, Sudhakar M. Reddy:
Forming multi-cycle tests for delay faults by concatenating broadside tests. VTS 2010: 51-56 - [c311]Dongok Kim, Irith Pomeranz, M. Enamul Amyeen, Srikanth Venkataraman:
Defect diagnosis based on DFM guidelines. VTS 2010: 206-211 - [c310]Irith Pomeranz, Sudhakar M. Reddy:
On multiple bridging faults. VTS 2010: 221-226 - 2009
- [c309]Irith Pomeranz, Sudhakar M. Reddy:
Dynamic test compaction for a random test generation procedure with input cube avoidance. ASP-DAC 2009: 672-677 - [c308]Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz:
Detectability of internal bridging faults in scan chains. ASP-DAC 2009: 678-683 - [c307]Irith Pomeranz, Sudhakar M. Reddy:
Fault Diagnosis under Transparent-Scan. Asian Test Symposium 2009: 29-34 - [c306]Gang Chen, Janusz Rajski, Sudhakar M. Reddy, Irith Pomeranz:
N-distinguishing Tests for Enhanced Defect Diagnosis. Asian Test Symposium 2009: 183-186 - [c305]Irith Pomeranz, Sudhakar M. Reddy:
Selection of a fault model for fault diagnosis based on unique responses. DATE 2009: 994-999 - [c304]Santiago Remersaro, Janusz Rajski, Sudhakar M. Reddy, Irith Pomeranz:
A scalable method for the generation of small test sets. DATE 2009: 1136-1141 - [c303]Irith Pomeranz, Sudhakar M. Reddy:
On-chip Generation of the Second Primary Input Vectors of Broadside Tests. DFT 2009: 38-46 - [c302]Irith Pomeranz, Sudhakar M. Reddy:
Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Functional Test Sequences. DFT 2009: 358-366 - [c301]Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz:
Improving the Detectability of Resistive Open Faults in Scan Cells. DFT 2009: 383-391 - [c300]Irith Pomeranz, Sudhakar M. Reddy:
Input Cubes with Lingering Synchronization Effects and their Use in Random Sequential Test Generation. ETS 2009: 87-92 - [c299]Irith Pomeranz, Sudhakar M. Reddy:
Partitioned n-detection test generation. ACM Great Lakes Symposium on VLSI 2009: 93-98 - [c298]Irith Pomeranz, Sudhakar M. Reddy:
Definition and application of approximate necessary assignments. ACM Great Lakes Symposium on VLSI 2009: 105-108 - [c297]Irith Pomeranz, Sudhakar M. Reddy:
State persistence: a property for guiding test generation. ACM Great Lakes Symposium on VLSI 2009: 523-528 - [c296]Irith Pomeranz, Sudhakar M. Reddy:
The Effect of Filling the Unspecified Values of a Test Set on the Test Set Quality. VLSI Design 2009: 215-220 - 2008
- [c295]Irith Pomeranz, Sudhakar M. Reddy:
Circuit lines for guiding the generation of random test sequences for synchronous sequential circuits. ASP-DAC 2008: 641-646 - [c294]Irith Pomeranz, Sudhakar M. Reddy:
Test vector chains for increased targeted and untargeted fault coverage. ASP-DAC 2008: 663-666 - [c293]Dongok Kim, Irith Pomeranz, M. Enamul Amyeen, Srikanth Venkataraman:
Prioritizing the Application of DFM Guidelines Based on the Detectability of Systematic Defects. ATS 2008: 217-220 - [c292]Sudhakar M. Reddy, Irith Pomeranz, Chen Liu:
On tests to detect via opens in digital CMOS circuits. DAC 2008: 840-845 - [c291]Irith Pomeranz, Sudhakar M. Reddy:
A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy. DATE 2008: 1166-1171 - [c290]Irith Pomeranz, Sudhakar M. Reddy:
A Same/Different Fault Dictionary: An Extended Pass/Fail Fault Dictionary with Improved Diagnostic Resolution. DATE 2008: 1474-1479 - [c289]Ilia Polian, Sudhakar M. Reddy, Irith Pomeranz, Xun Tang, Bernd Becker:
On Reducing Circuit Malfunctions Caused by Soft Errors. DFT 2008: 245-253 - [c288]Santiago Remersaro, Janusz Rajski, Thomas Rinderknecht, Sudhakar M. Reddy, Irith Pomeranz:
ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction. DFT 2008: 385-393 - [c287]Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz:
Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells. DFT 2008: 394-402 - [c286]Irith Pomeranz, Sudhakar M. Reddy:
Safe Fault Collapsing Based on Dominance Relations. ETS 2008: 7-12 - [c285]Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz:
An Enhanced Logic BIST Architecture for Online Testing. IOLTS 2008: 10-15 - [c284]Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz:
Detection of Internal Stuck-open Faults in Scan Chains. ITC 2008: 1-10 - [c283]Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu:
On Common-Mode Skewed-Load and Broadside Tests. VLSI Design 2008: 151-156 - [c282]Irith Pomeranz, Sudhakar M. Reddy:
Design-for-Testability for Improved Path Delay Fault Coverage of Critical Paths. VLSI Design 2008: 175-180 - [c281]Irith Pomeranz, Sudhakar M. Reddy:
Design-for-Testability for Synchronous Sequential Circuits that Maintains Functional Switching Activity. VLSI Design 2008: 181-186 - [c280]Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz:
On the Detectability of Scan Chain Internal Faults - An Industrial Case Study. VTS 2008: 79-84 - [c279]Irith Pomeranz, Sudhakar M. Reddy:
Synthesis for Broadside Testability of Transition Faults. VTS 2008: 221-226 - [c278]Irith Pomeranz, Sudhakar M. Reddy:
Expanded Definition of Functional Operation Conditions and its Effects on the Computation of Functional Broadside Tests. VTS 2008: 317-322 - 2007
- [c277]Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz:
Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes. ASP-DAC 2007: 817-822 - [c276]Irith Pomeranz, Praveen Parvathala, Srinivas Patil:
Estimating the Fault Coverage of Functional Test Sequences Without Fault Simulation. ATS 2007: 25-32 - [c275]Irith Pomeranz, Sudhakar M. Reddy:
Diagnostic Test Generation Targeting Equivalence Classes. ATS 2007: 301-306 - [c274]Irith Pomeranz, Sudhakar M. Reddy:
Enhanced Broadside Testing for Improved Transition Fault Coverage. ATS 2007: 479-484 - [c273]Irith Pomeranz, Sudhakar M. Reddy:
On test generation by input cube avoidance. DATE 2007: 522-527 - [c272]Irith Pomeranz, Sudhakar M. Reddy:
A-Diagnosis: A Complement to Z-Diagnosis. DFT 2007: 235-242 - [c271]Irith Pomeranz, Sudhakar M. Reddy:
Semi-Concurrent On-Line Testing of Transition Faults Through Output Response Comparison of Identical Circuits. DFT 2007: 457-455 - [c270]Irith Pomeranz, Sudhakar M. Reddy:
Diagnostic Test Generation Based on Subsets of Faults. ETS 2007: 151-158 - [c269]Dongok Kim, M. Enamul Amyeen, Srikanth Venkataraman, Irith Pomeranz, Swagato Basumallick, Berni Landau:
Testing for systematic defects based on DFM guidelines. ITC 2007: 1-10 - [c268]Irith Pomeranz, Sudhakar M. Reddy:
On the saturation of n-detection test sets with increased n. ITC 2007: 1-10 - [c267]Irith Pomeranz, Sudhakar M. Reddy:
Equivalence and Dominance Relations Between Fault Pairs and Their Use in Fault Pair Collapsing for Fault Diagnosis. VLSI Design 2007: 498-503 - [c266]Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski:
Low Shift and Capture Power Scan Tests. VLSI Design 2007: 793-798 - [c265]Irith Pomeranz, Sudhakar M. Reddy:
Functional Broadside Tests with Different Levels of Reachability. VLSI Design 2007: 799-804 - [c264]Irith Pomeranz, Sudhakar M. Reddy:
Autoscan-Invert: An Improved Scan Design without External Scan Inputs or Outputs. VTS 2007: 416-421 - 2006
- [c263]Irith Pomeranz, Srinivas Patil, Praveen Parvathala:
A Functional Fault Model with Implicit Fault Effect Propagation Requirements. ATS 2006: 95-102 - [c262]Irith Pomeranz:
To Overtest Or Not To Overtest - More Questions Than Answers. ATS 2006: 125 - [c261]Irith Pomeranz, Sudhakar M. Reddy:
On the Replacement of Scan Chain Inputs by Primary Input Vectors. ATS 2006: 175-182 - [c260]Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski:
A test pattern ordering algorithm for diagnosis with truncated fail data. DAC 2006: 399-404 - [c259]Irith Pomeranz, Sudhakar M. Reddy:
Generation of broadside transition fault test sets that detect four-way bridging faults. DATE 2006: 907-912 - [c258]Irith Pomeranz, Sudhakar M. Reddy:
Test compaction for transition faults under transparent-scan. DATE 2006: 1264-1269 - [c257]Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz:
Test Generation for Open Defects in CMOS Circuits. DFT 2006: 41-49 - [c256]Hangkyu Lee, Suriyaprakash Natarajan, Srinivas Patil, Irith Pomeranz:
Selecting High-Quality Delay Tests for Manufacturing Test and Debug. DFT 2006: 59-70 - [c255]Irith Pomeranz, Sudhakar M. Reddy:
Scan-Based Delay Fault Tests for Diagnosis of Transition Faults. DFT 2006: 419-427 - [c254]Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Bashir M. Al-Hashimi:
Enhancing Delay Fault Coverage through Low Power Segmented Scan. ETS 2006: 21-28 - [c253]Irith Pomeranz, Sudhakar M. Reddy:
Fault Collapsing for Transition Faults Using Extended Transition Faults. ETS 2006: 173-178 - [c252]Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz:
A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults. ETS 2006: 185-192 - [c251]Irith Pomeranz, Sudhakar M. Reddy:
A delay fault model for at-speed fault simulation and test generation. ICCAD 2006: 89-95 - [c250]Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz:
A Partitioning Technique for Identification of Error-Capturing Scan Cells in Scan-BIST. IOLTS 2006: 37-42 - [c249]Sungchul Park, Li Chen, Praveen Parvathala, Srinivas Patil, Irith Pomeranz:
A Functional Coverage Metric for Estimating the Gate-Level Fault Coverage of Functional Tests. ITC 2006: 1-10 - [c248]Irith Pomeranz, Sudhakar M. Reddy:
Fault Detection by Output Response Comparison of Identical Circuits Using Half-Frequency Compatible Sequences. ITC 2006: 1-10 - [c247]Santiago Remersaro, Xijiang Lin, Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski:
Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs. ITC 2006: 1-10 - [c246]Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski:
New Procedures to Identify Redundant Stuck-At Faults and Removal of Redundant Logic. VLSI Design 2006: 419-424 - [c245]Irith Pomeranz, Sudhakar M. Reddy:
The Cut Delay Fault Model for Guiding the Generation of n-Detection Test Sets for Transition Faults. VLSI Design 2006: 828-831 - [c244]Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy:
A Test Generation Procedure for Avoiding the Detection of Functionally Redundant Transition Faults. VTS 2006: 294-299 - [c243]Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski:
Scan Tests with Multiple Fault Activation Cycles for Delay Faults. VTS 2006: 343-348 - [c242]Bharath Seshadri, Irith Pomeranz, Srikanth Venkataraman, M. Enamul Amyeen, Sudhakar M. Reddy:
Dominance Based Analysis for Large Volume Production Fail Diagnosis. VTS 2006: 392-399 - [c241]Irith Pomeranz, Sudhakar M. Reddy:
On the Use of Functional Test Generation in Diagnostic Test Generation for Synchronous Sequential Circuits. V&D@FLoC 2006: 83-93 - 2005
- [c240]Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz:
Circuit Independent Weighted Pseudo-Random BIST Pattern Generator. Asian Test Symposium 2005: 132-137 - [c239]Narendra Devta-Prasanna, Sudhakar M. Reddy, Arun Gunda, P. Krishnamurthy, Irith Pomeranz:
Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions. Asian Test Symposium 2005: 202-207 - [c238]Irith Pomeranz:
N-detection under transparent-scan. DAC 2005: 129-134 - [c237]Irith Pomeranz, Sudhakar M. Reddy:
Worst-Case and Average-Case Analysis of n-Detection Test Sets. DATE 2005: 444-449 - [c236]Huaxing Tang, Gang Chen, Sudhakar M. Reddy, Chen Wang, Janusz Rajski, Irith Pomeranz:
Defect Aware Test Patterns. DATE 2005: 450-455 - [c235]Irith Pomeranz, Sudhakar M. Reddy:
The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits. DATE 2005: 1008-1013 - [c234]Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz:
On Generating Pseudo-Functional Delay Fault Tests for Scan Designs. DFT 2005: 398-405 - [c233]Irith Pomeranz, Sudhakar M. Reddy:
Recovery During Concurrent On-Line Testing of Identical Circuits. DFT 2005: 475-483 - [c232]Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Piet Engelke, Bernd Becker:
A unified fault model and test generation procedure for interconnect opens and bridges. ETS 2005: 22-27 - [c231]Irith Pomeranz, Sudhakar M. Reddy:
Using dummy bridging faults to define a reduced set of target faults. ETS 2005: 42-47 - [c230]Bharath Seshadri, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu:
Path-oriented transition fault test generation considering operating conditions. ETS 2005: 54-59 - [c229]Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz:
A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals. ICCD 2005: 471-474 - [c228]Yuan Cai, Sudhakar M. Reddy, Irith Pomeranz, Bashir M. Al-Hashimi:
Battery-aware dynamic voltage scaling in multiprocessor embedded system. ISCAS (1) 2005: 616-619 - [c227]Irith Pomeranz, Sudhakar M. Reddy:
Dynamic Test Compaction for Bridging Faults. ISQED 2005: 250-255 - [c226]Wei Li, Sudhakar M. Reddy, Irith Pomeranz:
On Reducing Peak Current and Power during Test. ISVLSI 2005: 156-161 - [c225]Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy:
Fault Diagnosis and Fault Model Aliasing. ISVLSI 2005: 206-211 - [c224]Irith Pomeranz, Sudhakar M. Reddy:
Forming N-detection test sets from one-detection test sets without test generation. ITC 2005: 9 - [c223]Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz:
Methods for improving transition delay fault coverage using broadside tests. ITC 2005: 10 - [c222]Irith Pomeranz, Sudhakar M. Reddy:
Tuple Detection for Path Delay Faults: A Method for Improving Test Set Quality. VLSI Design 2005: 41-46 - [c221]Huaxing Tang, Chen Wang, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Irith Pomeranz:
On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios. VLSI Design 2005: 59-64 - 2004
- [c220]Irith Pomeranz, Sudhakar M. Reddy:
Properties of Maximally Dominating Faults. Asian Test Symposium 2004: 106-111 - [c219]Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz:
Weighted Pseudo-Random BIST for N-Detection of Single Stuck-at Faults. Asian Test Symposium 2004: 178-183 - [c218]Irith Pomeranz, Sudhakar M. Reddy:
A Postprocessing Procedure of Test Enrichment for Path Delay Faults. Asian Test Symposium 2004: 448-453 - [c217]Wei Li, Sudhakar M. Reddy, Irith Pomeranz:
On test generation for transition faults with minimized peak power dissipation. DAC 2004: 504-509 - [c216]Irith Pomeranz:
On the generation of scan-based test sets with reachable states for testing under functional operation conditions. DAC 2004: 928-933 - [c215]Irith Pomeranz:
Scan-BIST based on transition probabilities. DAC 2004: 940-943 - [c214]Irith Pomeranz, Sudhakar M. Reddy:
Level of Similarity: A Metric for Fault Collapsing. DATE 2004: 56-61 - [c213]Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy, Bharath Seshadri:
Z-Sets and Z-Detections: Circuit Characteristics that Simplify Fault Diagnosis. DATE 2004: 68-75 - [c212]Irith Pomeranz, Sudhakar M. Reddy:
Reducing Fault Latency in Concurrent On-Line Testing by Using Checking Functions over Internal Lines. DFT 2004: 183-190 - [c211]Irith Pomeranz, Sudhakar M. Reddy:
Concurrent On-Line Testing of Identical Circuits Through Output Comparison Using Non-Identical Input Vectors. DFT 2004: 469-476 - [c210]Irith Pomeranz, Sudhakar M. Reddy:
On Undetectable Faults in Partial Scan Circuits Using Transparent-Scan. ICCD 2004: 82-84 - [c209]Yonsang Cho, Irith Pomeranz, Sudhakar M. Reddy:
Test Application Time Reduction for Scan Circuits Using Limited Scan Operations. ISQED 2004: 211-216 - [c208]Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy:
Scan BIST Targeting Transition Faults Using a Markov Source. ISQED 2004: 497-502 - [c207]Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy:
Z-DFD: Design-for-Diagnosability Based on the Concept of Z-Detection. ITC 2004: 489-497 - [c206]Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy, M. Enamul Amyeen:
Defect Diagnosis Based on Pattern-Dependent Stuck-At Faults. VLSI Design 2004: 475-480 - [c205]Irith Pomeranz, Sudhakar M. Reddy:
On Interconnecting Circuits with Multiple Scan Chains for Improved Test Data Compression. VLSI Design 2004: 741-744 - 2003
- [c204]Irith Pomeranz, Sudhakar M. Reddy:
A DFT Approach for Path Delay Faults in Interconnected Circuits. Asian Test Symposium 2003: 72-77 - [c203]Irith Pomeranz, Sudhakar M. Reddy:
Test Data Volume Reduction by Test Data Realignment. Asian Test Symposium 2003: 434-439 - [c202]Wei Li, Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz:
A scan BIST generation method using a markov source and partial bit-fixing. DAC 2003: 554-559 - [c201]Irith Pomeranz, Sudhakar M. Reddy:
On test data compression and n-detection test sets. DAC 2003: 748-751 - [c200]Irith Pomeranz, Sudhakar M. Reddy:
A New Approach to Test Generation and Test Compaction for Scan Circuits. DATE 2003: 11000-11005 - [c199]Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu:
On the Characterization of Hard-to-Detect Bridging Faults. DATE 2003: 11012-11019 - [c198]Irith Pomeranz, Sudhakar M. Reddy:
Test Data Compression Based on Output Dependence. DATE 2003: 11186-11187 - [c197]Bharath Seshadri, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu:
On path selection for delay fault testing considering operating conditions [logic IC testing]. ETW 2003: 141-146 - [c196]Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Jerzy Tyszer:
On Compacting Test Response Data Containing Unknown Values. ICCAD 2003: 855-862 - [c195]Irith Pomeranz, Sudhakar M. Reddy:
On Application of Output Masking to Undetectable Faults in Synchronous Sequential Circuits with Design-for-Testability Logic. ICCAD 2003: 867-873 - [c194]Gang Chen, Sudhakar M. Reddy, Irith Pomeranz:
Procedures for Identifying Untestable and Redundant Transition Faults in Synchronous Sequential Circuits. ICCD 2003: 36-41 - [c193]Irith Pomeranz, Sudhakar M. Reddy:
Static Test Compaction for Multiple Full-Scan Circuits. ICCD 2003: 393-396 - [c192]Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu, Seiji Kajihara, Irith Pomeranz:
A Method to Find Don't Care Values in Test Sequences for Sequential Circuits. ICCD 2003: 397- - [c191]Chaowen Yu, Wei Li, Sudhakar M. Reddy, Irith Pomeranz:
An Improved Markov Source Design for Scan BIST. IOLTS 2003: 106-110 - [c190]Mohamed A. Gomaa, Chad Scarbrough, Irith Pomeranz, T. N. Vijaykumar:
Transient-Fault Recovery for Chip Multiprocessors. ISCA 2003: 98-109 - [c189]Irith Pomeranz:
Reducing Test Data Volume Using Random-Testable and Periodic-Testable Scan Chains in Circuits with Multiple Scan Chains. ITC 2003: 441-450 - [c188]Masao Naruse, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu:
On-chip Compression of Output Responses with Unknown Values Using LFSR Reseeding. ITC 2003: 1060-1068 - [c187]Huaxing Tang, Sudhakar M. Reddy, Irith Pomeranz:
On Reducing Test Data Volume and Test Application Time for Multiple Scan Chain Designs. ITC 2003: 1079-1088 - [c186]Wei Zou, Chris Chu, Sudhakar M. Reddy, Irith Pomeranz:
Optimizing SOC Test Resources using Dual Sequences. VLSI-SOC 2003: 180-185 - [c185]Wei Zou, Chris C. N. Chu, Sudhakar M. Reddy, Irith Pomeranz:
Optimizing SOC Test Resources Using Dual Sequences. VLSI-SoC (Selected Papers) 2003: 181-196 - [c184]Irith Pomeranz, Sudhakar M. Reddy:
Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Non-Scan Sequential Test Sequences. VLSI Design 2003: 335-340 - [c183]Ganesh Venkataraman, Sudhakar M. Reddy, Irith Pomeranz:
GALLOP: Genetic Algorithm based Low Power FSM Synthesis by Simultaneous Partitioning and State Assignment. VLSI Design 2003: 533-538 - [c182]Irith Pomeranz, Sudhakar M. Reddy:
On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit. VTS 2003: 173-178 - [c181]Wei Zou, Sudhakar M. Reddy, Irith Pomeranz, Yu Huang:
SOC Test Scheduling Using Simulated Annealing. VTS 2003: 325-330 - [c180]Xiaoming Yu, M. Enamul Amyeen, Srikanth Venkataraman, Ruifeng Guo, Irith Pomeranz:
Concurrent Execution of Diagnostic Fault Simulation and Equivalence Identification During Diagnostic Test Generation. VTS 2003: 351-358 - [c179]Irith Pomeranz, Sudhakar M. Reddy, Yervant Zorian:
A Test Interface for Built-In Test of Non-Isolated Scanned Cores. VTS 2003: 371-378 - 2002
- [c178]Yun Shao, Irith Pomeranz, Sudhakar M. Reddy:
On Generating High Quality Tests for Transition Faults. Asian Test Symposium 2002: 1 - [c177]Ilia Polian, Irith Pomeranz, Bernd Becker:
Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests. Asian Test Symposium 2002: 2-14 - [c176]Irith Pomeranz, Sudhakar M. Reddy:
Improving the Efficiency of Static Compaction Based on Chronological Order Enumeration of Test Sequences. Asian Test Symposium 2002: 61-66 - [c175]Seiji Kajihara, Kenjiro Taniguchi, Kohei Miyase, Irith Pomeranz, Sudhakar M. Reddy:
Test Data Compression Using Don?t-Care Identification and Statistical Encoding. Asian Test Symposium 2002: 67- - [c174]Irith Pomeranz, Sudhakar M. Reddy:
A Partitioning and Storage Based Built-In Test Pattern Generation Method for Delay Faults in Scan Circuits. Asian Test Symposium 2002: 110-115 - [c173]Irith Pomeranz, Sandip Kundu, Sudhakar M. Reddy:
On output response compression in the presence of unknown output values. DAC 2002: 255-258 - [c172]Irith Pomeranz, Sudhakar M. Reddy:
Test Enrichment for Path Delay Faults Using Multiple Sets of Target Faults. DATE 2002: 722-729 - [c171]Irith Pomeranz, Janusz Rajski, Sudhakar M. Reddy:
Finding a Common Fault Response for Diagnosis during Silicon Debug. DATE 2002: 1116 - [c170]Irith Pomeranz, Yervant Zorian:
Fault Isolation Using Tests for Non-Isolated Blocks. DATE 2002: 1123 - [c169]Irith Pomeranz, Sudhakar M. Reddy:
Properties of Output Sequences and their Use in Guiding Property-Based Test Generation for Synchronous Sequential Circuits. DELTA 2002: 377-381 - [c168]Seiji Kajihara, Kenjiro Taniguchi, Irith Pomeranz, Sudhakar M. Reddy:
Test Data Compression Using Don't-Care Identification and Statistical Encoding. DELTA 2002: 413-416 - [c167]Yun Shao, Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara:
On selecting testable paths in scan designs. ETW 2002: 53-58 - [c166]Irith Pomeranz, Sudhakar M. Reddy:
On undetectable faults in partial scan circuits. ICCAD 2002: 82-86 - [c165]Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski:
Conflict driven techniques for improving deterministic test pattern generation. ICCAD 2002: 87-93 - [c164]Kohei Miyase, Seiji Kajihara, Irith Pomeranz, Sudhakar M. Reddy:
Don't-Care Identification on Specific Bits of Test Patterns. ICCD 2002: 194-199 - [c163]Irith Pomeranz, Sudhakar M. Reddy:
On the Coverage of Delay Faults in Scan Designs with Multiple Scan Chains. ICCD 2002: 206-209 - [c162]Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz:
A Low Power Pseudo-Random BIST Technique. ICCD 2002: 468-473 - [c161]Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz:
A Low Power Pseudo-Random BIST Technique. IOLTW 2002: 140- - [c160]T. N. Vijaykumar, Irith Pomeranz, Karl Cheng:
Transient-Fault Recovery Using Simultaneous Multithreading. ISCA 2002: 87-98 - [c159]Sudhakar M. Reddy, Irith Pomeranz, Huaxing Tang, Seiji Kajihara, Kozo Kinoshita:
On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout. ITC 2002: 83-89 - [c158]Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz:
Pseudo Random Patterns Using Markov Sources for Scan BIST. ITC 2002: 1013-1021 - [c157]Irith Pomeranz, Sudhakar M. Reddy:
A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits. ASP-DAC/VLSI Design 2002: 677-682 - [c156]Yun Shao, Irith Pomeranz, Sudhakar M. Reddy:
Path Delay Fault Test Generation for Standard Scan Designs Using State Tuples. ASP-DAC/VLSI Design 2002: 767-772 - [c155]Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz:
On Test Data Volume Reduction for Multiple Scan Chain Designs. VTS 2002: 103-110 - [c154]M. Enamul Amyeen, Irith Pomeranz, W. Kent Fuchs:
Theorems for Efficient Identification of Indistinguishable Fault Pairs in Synchronous Sequential Circuits. VTS 2002: 181-186 - 2001
- [c153]Irith Pomeranz:
On Pass/Fail Dictionaries for Scan Circuits . Asian Test Symposium 2001: 51-56 - [c152]Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz:
On Improving a Fault Simulation Based Test Generator for Synchronous Sequential Circuits. Asian Test Symposium 2001: 82- - [c151]Irith Pomeranz, Sudhakar M. Reddy:
A Postprocessing Procedure to Reduce the Number of Different Test Lengths in a Test Set for Scan Circuits. Asian Test Symposium 2001: 131-136 - [c150]Yun Shao, Sudhakar M. Reddy, Seiji Kajihara, Irith Pomeranz:
An Efficient Method to Identify Untestable Path Delay Faults. Asian Test Symposium 2001: 233-238 - [c149]Irith Pomeranz, Sudhakar M. Reddy, Xijiang Lin:
Experimental Results of Forward-Looking Reverse Order Fault Simulation on Industrial Circuits with Scan. Asian Test Symposium 2001: 467 - [c148]Irith Pomeranz:
Random Limited-Scan to Improve Random Pattern Testing of Scan Circuits. DAC 2001: 145-150 - [c147]Irith Pomeranz, Sudhakar M. Reddy:
An Approach to Test Compaction for Scan Circuits that Enhances At-Speed Testing. DAC 2001: 156-161 - [c146]Irith Pomeranz, Sudhakar M. Reddy:
Sequence reordering to improve the levels of compaction achievable by static compaction procedures. DATE 2001: 214-218 - [c145]Irith Pomeranz, Sudhakar M. Reddy:
Definitions of the numbers of detections of target faults and their effectiveness in guiding test generation for high defect coverage. DATE 2001: 504-508 - [c144]Irith Pomeranz, Sudhakar M. Reddy:
ITEM: an iterative improvement test generation procedure for synchronous sequential circuits. ACM Great Lakes Symposium on VLSI 2001: 13-18 - [c143]Irith Pomeranz, Sudhakar M. Reddy:
Estimating the relative single stuck-at fault coverage of test sets for a combinational logic block from its functional description. HLDVT 2001: 31-35 - [c142]Chen Wang, Irith Pomeranz, Sudhakar M. Reddy:
REDI: An Efficient Fault Oriented Procedure to Identify Redundant Faults in Combinational Logic Circuits. ICCAD 2001: 370-374 - [c141]Irith Pomeranz, Sudhakar M. Reddy:
COREL: A Dynamic Compaction Procedure for Synchronous Sequential Circuits with Repetition and Local Static Compaction. ICCD 2001: 142-147 - [c140]Irith Pomeranz, Sudhakar M. Reddy:
A Partitioning and Storage Based Built-in Test Pattern Generation Method for Synchronous Sequential Circuits. ICCD 2001: 148-153 - [c139]Irith Pomeranz, Sudhakar M. Reddy:
A method to enhance the fault coverage obtained by output response comparison of identical circuits. ITC 2001: 196-203 - [c138]Irith Pomeranz, Sudhakar M. Reddy:
On improving the stuck-at fault coverage of functional test sequences by using limited-scan operations. ITC 2001: 211-220 - [c137]Xijiang Lin, Janusz Rajski, Irith Pomeranz, Sudhakar M. Reddy:
On static test compaction and test pattern ordering for scan designs. ITC 2001: 1088-1097 - [c136]Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy:
On Improving Static Test Compaction for Sequential Circuits. VLSI Design 2001: 111-116 - [c135]M. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana:
Fault Equivalence Identification Using Redundancy Information and Static and Dynamic Extraction. VTS 2001: 124-130 - [c134]Irith Pomeranz, Sudhakar M. Reddy:
On the Use of Fault Dominance in n-Detection Test Generation. VTS 2001: 352-357 - 2000
- [c133]Irith Pomeranz, Sudhakar M. Reddy:
On the feasibility of fault simulation using partial circuit descriptions. Asian Test Symposium 2000: 108-113 - [c132]Seiji Kajihara, Takashi Shimono, Irith Pomeranz, Sudhakar M. Reddy:
Enhanced untestable path analysis using edge graphs. Asian Test Symposium 2000: 139-144 - [c131]Irith Pomeranz, Sudhakar M. Reddy:
Reducing test application time for full scan circuits by the addition of transfer sequences. Asian Test Symposium 2000: 317-322 - [c130]Irith Pomeranz, Sudhakar M. Reddy:
On diagnosis of pattern-dependent delay faults. DAC 2000: 59-62 - [c129]Irith Pomeranz, Sudhakar M. Reddy:
Built-In Generation of Weighted Test Sequences for Synchronous Sequential Circuits. DATE 2000: 298-304 - [c128]Irith Pomeranz, Sudhakar M. Reddy:
Functional Test Generation for Full Scan Circuits. DATE 2000: 396-401 - [c127]Irith Pomeranz, Sudhakar M. Reddy:
Test-Point Insertion to Enhance Test Compaction for Scan Designs. DSN 2000: 375-381 - [c126]Irith Pomeranz, Sudhakar M. Reddy:
On the use of multiple fault detection times in a method for built-in test pattern generation for synchronous sequential circuits. ETW 2000: 144-149 - [c125]Yu Huang, Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski:
Improving the Proportion of At-Speed Tests in Scan BIST. ICCAD 2000: 459-463 - [c124]Irith Pomeranz, Sudhakar M. Reddy:
Simulation Based Test Generation for Scan Designs. ICCAD 2000: 544-549 - [c123]Irith Pomeranz, Sudhakar M. Reddy:
Sensitivity Levels of Test Patterns and Their Usefulness in Simulation-Based Test Generation. ICCD 2000: 389-394 - [c122]Irith Pomeranz, Sudhakar M. Reddy:
On Test Application Time and Defect Detection Capabilities of Test Sets for Scan Designs. ICCD 2000: 395-400 - [c121]Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara, Atsushi Murakami, Sadami Takeoka, Mitsuyasu Ohta:
On validating data hold times for flip-flops in sequential circuits. ITC 2000: 317-325 - [c120]Atsushi Murakami, Seiji Kajihara, Tsutomu Sasao, Irith Pomeranz, Sudhakar M. Reddy:
Selection of potentially testable path delay faults for test generation. ITC 2000: 376-384 - [c119]Irith Pomeranz, Sudhakar M. Reddy:
Fault diagnosis based on parameters of output responses. PRDC 2000: 139-147 - [c118]Hideyuki Ichihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy:
Test Transformation to Improve Compaction by Statistical Encoding. VLSI Design 2000: 294-299 - [c117]Irith Pomeranz, Sudhakar M. Reddy:
On Synchronizing Sequences and Unspecified Values in Output Responses of Synchronous Sequential Circuits. VLSI Design 2000: 392-397 - [c116]Xijiang Lin, Wu-Tung Cheng, Irith Pomeranz, Sudhakar M. Reddy:
SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration. VTS 2000: 205-212 - 1999
- [c115]Irith Pomeranz, Sudhakar M. Reddy:
Vector-Based Functional Fault Models for Delay Faults. Asian Test Symposium 1999: 41-46 - [c114]Irith Pomeranz, Sudhakar M. Reddy:
Pattern Sensitivity: A Property to Guide Test Generation for Combinational Circuits. Asian Test Symposium 1999: 75-80 - [c113]Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz:
Proptest: A Property Based Test Pattern Generator for Sequential Circuits Using Test Compaction. DAC 1999: 653-659 - [c112]Irith Pomeranz, Sudhakar M. Reddy:
Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Test Subsequences. DAC 1999: 754-759 - [c111]Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy:
Full Scan Fault Coverage With Partial Scan. DATE 1999: 468-472 - [c110]Irith Pomeranz, Sudhakar M. Reddy:
On avoiding undetectable faults during test generation. ETW 1999: 90-95 - [c109]Irith Pomeranz, Sudhakar M. Reddy:
PASTA: Partial Scan to Enhance Test Compaction. Great Lakes Symposium on VLSI 1999: 4-7 - [c108]Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy:
Techniques for improving the efficiency of sequential circuit test generation. ICCAD 1999: 147-151 - [c107]Irith Pomeranz, Sudhakar M. Reddy:
An approach for improving the levels of compaction achieved by vector omission. ICCAD 1999: 463-466 - [c106]Irith Pomeranz, Sudhakar M. Reddy:
Fault Simulation Based Test Generation for Combinational Circuits Using Dynamically Selected Sub-Circuits. ICCD 1999: 412-417 - [c105]Irith Pomeranz, Sudhakar M. Reddy:
On achieving complete coverage of delay faults in full scan circuits using locally available lines. ITC 1999: 923-931 - [c104]Yun Shao, Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz:
The effects of test compaction on fault diagnosis. ITC 1999: 1083-1089 - [c103]Irith Pomeranz, Sudhakar M. Reddy:
VERSE: A Vector Replacement Procedure for Improving Test Compaction in Synchronous Sequential Circuits. VLSI Design 1999: 250-255 - [c102]Irith Pomeranz, Yervant Zorian:
Testing of Non-Isolated Embedded Legacy Cores and their Surrounding Logic. VTS 1999: 41-48 - [c101]Irith Pomeranz, Sudhakar M. Reddy:
A Flexible Path Selection Procedure for Path Delay Fault Testing. VTS 1999: 152-159 - [c100]Irith Pomeranz, Sudhakar M. Reddy:
On n-Detection Test Sets and Variable n-Detection Test Sets for Transition Faults. VTS 1999: 173-181 - [c99]M. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana:
Implication and Evaluation Techniques for Proving Fault Equivalence. VTS 1999: 201-213 - [c98]Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy:
A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits. VTS 1999: 260-267 - [c97]Sudhakar M. Reddy, Irith Pomeranz, Nadir Z. Basturkmen, Xijiang Lin:
Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits. VTS 1999: 275-283 - 1998
- [c96]Irith Pomeranz, Sudhakar M. Reddy:
Static Test Compaction for Scan-Based Designs to Reduce Test Application Time. Asian Test Symposium 1998: 198-203 - [c95]Irith Pomeranz, Sudhakar M. Reddy:
Test Generation for Synchronous Sequential Circuits to Reduce Storage Requirements. Asian Test Symposium 1998: 446-451 - [c94]Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy:
On Speeding-Up Vector Restoration Based Static Compaction of Test Sequences for Sequential Circuits . Asian Test Symposium 1998: 467-471 - [c93]Irith Pomeranz, W. Kent Fuchs:
A Diagnostic Test Generation Procedure for Combinational Circuits Based on Test Elimination. Asian Test Symposium 1998: 486-491 - [c92]Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy:
Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration. DATE 1998: 583-587 - [c91]Irith Pomeranz, Sudhakar M. Reddy:
A Synthesis Procedure for Flexible Logic Functions. DATE 1998: 973-974 - [c90]Irith Pomeranz, Sudhakar M. Reddy:
Design-for-Testability for Synchronous Sequential Circuits using Locally Available Lines. DATE 1998: 983-984 - [c89]Irith Pomeranz, Sudhakar M. Reddy:
A Generalized Test Generation Procedure for Path Delay Faults. FTCS 1998: 274-283 - [c88]Irith Pomeranz, Sudhakar M. Reddy:
Test Compaction for Synchronous Sequential Circuits by Test Sequence Recycling. Great Lakes Symposium on VLSI 1998: 216-221 - [c87]Irith Pomeranz, Sudhakar M. Reddy:
Improved built-in test pattern generators based on comparison units for synchronous sequential circuits. ICCD 1998: 26-31 - [c86]Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy:
On finding undetectable and redundant faults in synchronous sequential circuits. ICCD 1998: 498-503 - [c85]Irith Pomeranz, Sudhakar M. Reddy:
A diagnostic test generation procedure for synchronous sequential circuits based on test elimination. ITC 1998: 1074-1083 - [c84]Irith Pomeranz, Sudhakar M. Reddy:
On Test Compaction Objectives for Combinational and Sequential Circuits. VLSI Design 1998: 279-284 - [c83]Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy:
MIX: A Test Generation System for Synchronous Sequential Circuits. VLSI Design 1998: 456-463 - [c82]Irith Pomeranz, Sudhakar M. Reddy:
On Synchronizing Sequences and Test Sequence Partitioning. VTS 1998: 158-167 - [c81]Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy:
On Removing Redundant Faults in Synchronous Sequential Circuits. VTS 1998: 168-175 - [c80]Irith Pomeranz, Sudhakar M. Reddy:
Stuck-At Tuple-Detection: A Fault Model Based on Stuck-At Faults for Improved Defect Coverage. VTS 1998: 289-295 - 1997
- [c79]Irith Pomeranz, Sudhakar M. Reddy:
On the Compaction of Test Sets Produced by Genetic Optimization. Asian Test Symposium 1997: 4-9 - [c78]Irith Pomeranz, Sudhakar M. Reddy:
TEMPLATES: A Test Generation Procedure for Synchronous Sequential Circuits. Asian Test Symposium 1997: 74- - [c77]Irith Pomeranz, Sudhakar M. Reddy:
Fault Simulation under the Multiple Observation Time Approach using Backward Implications. DAC 1997: 608-613 - [c76]Irith Pomeranz, Sudhakar M. Reddy:
On improving genetic optimization based test generation. ED&TC 1997: 506-511 - [c75]Irith Pomeranz, Sudhakar M. Reddy:
On the use of reset to increase the testability of interconnected finite-state machines. ED&TC 1997: 554-559 - [c74]Irith Pomeranz, Sudhakar M. Reddy:
ACTIV-LOCSTEP: A Test Generation Procedure Based on Logic Simulation and Fault Activation. FTCS 1997: 144-151 - [c73]Irith Pomeranz, Sudhakar M. Reddy:
On Generating Test Sets that Remain Valid in the Presence of Undetected Faults. Great Lakes Symposium on VLSI 1997: 20-25 - [c72]Irith Pomeranz, Sudhakar M. Reddy:
Built-in test generation for synchronous sequential circuits. ICCAD 1997: 421-426 - [c71]Irith Pomeranz, Sudhakar M. Reddy:
Vector Restoration Based Static Compaction of Test Sequences for Synchronous Sequential Circuits. ICCD 1997: 360-365 - [c70]Seiji Kajihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy:
A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths. VLSI Design 1997: 82-87 - [c69]Irith Pomeranz, Sudhakar M. Reddy:
On the Detection of Reset Faults in Synchronous Sequential Circuits. VLSI Design 1997: 470-474 - [c68]Irith Pomeranz, Sudhakar M. Reddy:
On Full Reset as a Design-For-Testability Technique. VLSI Design 1997: 534-536 - [c67]Irith Pomeranz, Sudhakar M. Reddy:
EXTEST: a method to extend test sequences of synchronous sequential circuits to increase the fault coverage. VTS 1997: 329-335 - [c66]Irith Pomeranz, Sudhakar M. Reddy:
On n-detection test sequences for synchronous sequential circuits343. VTS 1997: 336-343 - 1996
- [c65]Irith Pomeranz, Sudhakar M. Reddy:
On Test Generation for Interconnected Finite-State Machines: The Input Sequence Propagation Problem. Asian Test Symposium 1996: 16-21 - [c64]Irith Pomeranz, Sudhakar M. Reddy:
Low-Complexity Fault Diagnosis Under the Multiple Observation Time Testing Approach. Asian Test Symposium 1996: 226-231 - [c63]Irith Pomeranz, Sudhakar M. Reddy:
On Static Compaction of Test Sequences for Synchronous Sequential Circuits. DAC 1996: 215-220 - [c62]Irith Pomeranz, Sudhakar M. Reddy:
On Test Generation for Interconnected Finite-State Machines - The Output Sequence Justification Problem. ED&TC 1996: 380-387 - [c61]Irith Pomeranz, Sudhakar M. Reddy:
Dynamic Test Compaction for Synchronous Sequential Circuits using Static Compaction Techniques. FTCS 1996: 53-61 - [c60]Irith Pomeranz, Sudhakar M. Reddy, Janak H. Patel:
On Double Transition Faults as a Delay Fault Model. Great Lakes Symposium on VLSI 1996: 282-287 - [c59]Irith Pomeranz, Sudhakar M. Reddy:
Fault Location Based on Circuit Partitioning. ICCD 1996: 242-247 - [c58]Elizabeth M. Rudnick, Janak H. Patel, Irith Pomeranz:
On Potential Fault Detection in Sequential Circuits. ITC 1996: 142-149 - [c57]Irith Pomeranz, Sudhakar M. Reddy:
On Cancelling the Effects of Logic Sharing for Improved Path Delay Fault Testability. ITC 1996: 357-366 - [c56]Irith Pomeranz, Nirmal R. Saxena, Richard Reeve, Paritosh Kulkarni, Yan A. Li:
Generation of Test Cases for Hardware Design Verification of a Super-Scalar Fetch Processor. ITC 1996: 904-913 - [c55]Irith Pomeranz, Sudhakar M. Reddy:
On Finding Functionally Identical and Functionally Opposite Lines in Combinational Logic Circuits. VLSI Design 1996: 254-259 - [c54]Yuan Lu, Irith Pomeranz:
Synchronization of large sequential circuits by partial reset. VTS 1996: 93-98 - [c53]Prasanti Uppaluri, Uwe Sparmann, Irith Pomeranz:
On minimizing the number of test points needed to achieve complete robust path delay fault testability. VTS 1996: 288-295 - [c52]Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara:
On the effects of test compaction on defect coverage. VTS 1996: 430-437 - 1995
- [c51]Irith Pomeranz, Sudhakar M. Reddy:
Static compaction for two-pattern test sets. Asian Test Symposium 1995: 222-228 - [c50]Irith Pomeranz, Sudhakar M. Reddy:
On Synthesis-for-Testability of Combinational Logic Circuits. DAC 1995: 126-132 - [c49]Irith Pomeranz, Sudhakar M. Reddy:
On generating compact test sequences for synchronous sequential circuits. EURO-DAC 1995: 105-110 - [c48]Irith Pomeranz, Sudhakar M. Reddy:
LOCSTEP: A Logic Simulation Based Test Generation Procedure. FTCS 1995: 110-119 - [c47]Irith Pomeranz, Sudhakar M. Reddy:
Functional test generation for delay faults in combinational circuits. ICCAD 1995: 687-694 - [c46]Irith Pomeranz, Sudhakar M. Reddy:
Test generation for multiple state-table faults in finite-state machines. ICCD 1995: 292-297 - [c45]Irith Pomeranz, Sudhakar M. Reddy:
Low-Complexity Fault Simulation under the Multiplie Observation Time Testing Approach. ITC 1995: 272-281 - [c44]Sitaran Yadavalli, Irith Pomeranz, Sudhakar M. Reddy:
MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level. VLSI Design 1995: 110-115 - [c43]Remata S. Reddy, Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara:
Compact test generation for bridging faults under IDDQ testing. VTS 1995: 310-316 - 1994
- [c42]Irith Pomeranz, Sudhakar M. Reddy:
Design-for-Testability for Path Delay Faults in Large Combinatorial Circuits Using Test-Points. DAC 1994: 358-364 - [c41]Irith Pomeranz, Sudhakar M. Reddy:
On Improving Fault Diagnosis for Synchronous Sequential Circuits. DAC 1994: 504-509 - [c40]Sudhakar M. Reddy, Irith Pomeranz, Rahul Jain:
On Codeword Testing of Two-Rail and Parity TSC Checkers. FTCS 1994: 116-125 - [c39]Prasanti Uppaluri, Irith Pomeranz, Sudhakar M. Reddy:
Test Pattern Generation for Path Delay Faults in Synchronous Sequential Circuits Using Multiple Fast Clocks and Multiple Observations Times. FTCS 1994: 456-465 - [c38]Irith Pomeranz, Sudhakar M. Reddy:
On testing delay faults in macro-based combinational circuits. ICCAD 1994: 332-339 - [c37]Irith Pomeranz, Sudhakar M. Reddy:
On error correction in macro-based circuits. ICCAD 1994: 568-575 - [c36]Irith Pomeranz, Sudhakar M. Reddy:
On Achieving Complete Testability of Synchronous Sequential Circuits with Synchronizing Sequences. ITC 1994: 1007-1016 - [c35]Irith Pomeranz, Sudhakar M. Reddy:
On Determining Symmetries in Inputs of Logic Circuits. VLSI Design 1994: 255-260 - [c34]Irith Pomeranz, Sudhakar M. Reddy:
On identifying undetectable and redundant faults in synchronous sequential circuits. VTS 1994: 8-14 - [c33]Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy:
On compacting test sets by addition and removal of test vectors. VTS 1994: 202-207 - 1993
- [c32]Irith Pomeranz, Sudhakar M. Reddy:
INCREDYBLE-TG: INCREmental DYnamic test generation based on LEarning. DAC 1993: 80-85 - [c31]Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy:
Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits. DAC 1993: 102-106 - [c30]Irith Pomeranz, Sudhakar M. Reddy, Prasanti Uppaluri:
NEST: A Non-Enumerative Test Generation Method for Path Delay Faults in Combinational Circuits. DAC 1993: 439-445 - [c29]Irith Pomeranz, Sudhakar M. Reddy:
A method for diagnosing implementation errors in synchronous sequential circuits and its implications on synthesis. EURO-DAC 1993: 252-258 - [c28]Venkataramana Kommu, Irith Pomeranz:
GAFPGA: Genetic algorithm for FPGA technology mapping. EURO-DAC 1993: 300-305 - [c27]Irith Pomeranz, Sudhakar M. Reddy:
EXOP (Extended Operation): A New Logical Fault Model for Digital Circuits. FTCS 1993: 166-175 - [c26]Irith Pomeranz, Sudhakar M. Reddy, Janak H. Patel:
Theory and Practice of Sequential Machine Testing and Testability. FTCS 1993: 330-337 - [c25]Irith Pomeranz, Sudhakar M. Reddy:
Design and Synthesis for Testability of Synchronous Sequential Circuits Based on Strong-Connectivity. FTCS 1993: 492-501 - [c24]Irith Pomeranz, Sudhakar M. Reddy:
Test generation for path delay faults based on learning. ICCAD 1993: 428-435 - [c23]Irith Pomeranz, Sudhakar M. Reddy:
On diagnosis and correction of design errors. ICCAD 1993: 500-507 - [c22]Paul G. Ryan, W. Kent Fuchs, Irith Pomeranz:
Fault dictionary compression and equivalence class computation for sequential circuits. ICCAD 1993: 508-511 - [c21]Irith Pomeranz, Sudhakar M. Reddy:
A Learning-Based Method to Match a Test Pattern Generator to a Circuit-Under-Test. ITC 1993: 998-1007 - [c20]Irith Pomeranz, Sudhakar M. Reddy:
On the Generation of Weights for Weighted Pseudo Random Testing. VLSI Design 1993: 69-72 - [c19]Irith Pomeranz, Sudhakar M. Reddy:
Aliasing computation using fault simulation with fault dropping. VTS 1993: 282-288 - 1992
- [c18]Irith Pomeranz, Sudhakar M. Reddy:
At-Speed Delay Testing of Synchronous Sequential Circuits. DAC 1992: 177-181 - [c17]Irith Pomeranz, Kwang-Ting Cheng:
State Assignment Using Input/Output Functions. DAC 1992: 573-577 - [c16]Irith Pomeranz, Lakshmi N. Reddy, Sudhakar M. Reddy:
SPADES: a simulator for path delay faults in sequential circuits. EURO-DAC 1992: 428-435 - [c15]Irith Pomeranz, Sudhakar M. Reddy:
A Divide-And-Conquer Approach to Test Generation for Large Synchronous Sequential Circuits. FTCS 1992: 230-237 - [c14]Niraj K. Jha, Irith Pomeranz, Sudhakar M. Reddy, Robert J. Miller:
Synthesis of Multi-Level Combinational Circuits for Complete Robust Path Delay Fault Testability. FTCS 1992: 280-287 - [c13]Irith Pomeranz, Sudhakar M. Reddy:
On the generation of small dictionaries for fault location. ICCAD 1992: 272-279 - [c12]Irith Pomeranz, Sudhakar M. Reddy:
An efficient non-enumerative method to estimate path delay fault coverage. ICCAD 1992: 560-567 - [c11]Lakshmi N. Reddy, Irith Pomeranz, Sudhakar M. Reddy:
COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits. ICCAD 1992: 568-574 - [c10]Venkataramana Kommu, Irith Pomeranz:
Effect of Communication in a Parallel Genetic Algorithm. ICPP (3) 1992: 310-317 - [c9]Irith Pomeranz, Sudhakar M. Reddy:
3-Weight Pseudo-Random Test Generation Based on a Deterministic Test Set. VLSI Design 1992: 148-153 - [c8]Irith Pomeranz, Sudhakar M. Reddy:
Generalization of independent faults for transition faults. VTS 1992: 7-12 - 1991
- [c7]Irith Pomeranz, Sudhakar M. Reddy:
On Achieving a Complete Fault Coverage for Sequential Machines Using the Transition Fault Model. DAC 1991: 341-346 - [c6]Irith Pomeranz, Sudhakar M. Reddy:
Test Generation for Synchronous Sequential Circuits Using Multiple Observation Times. FTCS 1991: 52-59 - [c5]Irith Pomeranz, Sudhakar M. Reddy:
Test Generation for Synchronous Sequential Circuits Based on Fault Extraction. ICCAD 1991: 450-453 - [c4]Irith Pomeranz, Sudhakar M. Reddy, Lakshmi N. Reddy:
Increasing Fault Coverage for Synchronous Sequential Circuits by the Multiple Observation Time Test Strategy. ICCAD 1991: 454-457 - [c3]Irith Pomeranz, Sudhakar M. Reddy:
Testing of Fault-Tolerant Hardware. Fault-Tolerant Computing Systems 1991: 148-159 - [c2]Irith Pomeranz, Lakshmi N. Reddy, Sudhakar M. Reddy:
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits. ITC 1991: 194-203 - [c1]Irith Pomeranz, Sudhakar M. Reddy:
Achieving Complete Delay Fault Testability by Extra Inputs. ITC 1991: 273-282
Informal and Other Publications
- 2007
- [i2]Irith Pomeranz, Sudhakar M. Reddy:
The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits. CoRR abs/0710.4637 (2007) - [i1]Irith Pomeranz, Sudhakar M. Reddy:
Worst-Case and Average-Case Analysis of n-Detection Test Sets. CoRR abs/0710.4735 (2007)
Coauthor Index
[j255] [j164] [j156] [j151] [j150] [j149] [j148] [j147] [j143] [j142] [j141] [j140] [j139] [j138] [j137] [j136] [j135] [j134] [j133] [j132] [j131] [j130] [j129] [j128] [j127] [j126] [j125] [j124] [j123] [j122] [j121] [j120] [j119] [j118] [j117] [j116] [j115] [j114] [j113] [j112] [j111] [j110] [j109] [j108] [j107] [j106] [j105] [j104] [j103] [j102] [j101] [j100] [j98] [j97] [j96] [j94] [j93] [j92] [j91] [j90] [j89] [j88] [j87] [j86] [j85] [j84] [j83] [j82] [j81] [j80] [j79] [j76] [j75] [j74] [j72] [j71] [j69] [j68] [j66] [j65] [j64] [j63] [j62] [j61] [j60] [j59] [j58] [j57] [j56] [j54] [j53] [j52] [j50] [j49] [j48] [j47] [j46] [j45] [j44] [j43] [j42] [j41] [j40] [j39] [j38] [j37] [j36] [j35] [j34] [j33] [j32] [j31] [j30] [j29] [j28] [j27] [j26] [j25] [j24] [j23] [j21] [j20] [j19] [j18] [j17] [j16] [j15] [j14] [j13] [j12] [j11] [j10] [j9] [j8] [j7] [j6] [j4] [c387] [c367] [c336] [c335] [c333] [c330] [c329] [c323] [c322] [c321] [c320] [c319] [c318] [c317] [c316] [c315] [c314] [c313] [c312] [c310] [c309] [c308] [c307] [c306] [c305] [c304] [c303] [c302] [c301] [c300] [c299] [c298] [c297] [c296] [c295] [c294] [c292] [c291] [c290] [c289] [c288] [c287] [c286] [c285] [c284] [c283] [c282] [c281] [c280] [c279] [c278] [c277] [c275] [c274] [c273] [c272] [c271] [c270] [c268] [c267] [c266] [c265] [c264] [c261] [c260] [c259] [c258] [c257] [c255] [c254] [c253] [c252] [c251] [c250] [c248] [c247] [c246] [c245] [c244] [c243] [c242] [c241] [c240] [c239] [c237] [c236] [c235] [c234] [c233] [c232] [c231] [c230] [c229] [c228] [c227] [c226] [c225] [c224] [c223] [c222] [c221] [c220] [c219] [c218] [c217] [c214] [c213] [c212] [c211] [c210] [c209] [c208] [c207] [c206] [c205] [c204] [c203] [c202] [c201] [c200] [c199] [c198] [c197] [c196] [c195] [c194] [c193] [c191] [c188] [c187] [c186] [c185] [c184] [c183] [c182] [c181] [c179] [c178] [c176] [c175] [c174] [c173] [c172] [c171] [c169] [c168] [c167] [c166] [c165] [c164] [c163] [c162] [c161] [c159] [c158] [c157] [c156] [c155] [c152] [c151] [c150] [c149] [c147] [c146] [c145] [c144] [c143] [c142] [c141] [c140] [c139] [c138] [c137] [c136] [c134] [c133] [c132] [c131] [c130] [c129] [c128] [c127] [c126] [c125] [c124] [c123] [c122] [c121] [c120] [c119] [c118] [c117] [c116] [c115] [c114] [c113] [c112] [c111] [c110] [c109] [c108] [c107] [c106] [c105] [c104] [c103] [c101] [c100] [c98] [c97] [c96] [c95] [c94] [c92] [c91] [c90] [c89] [c88] [c87] [c86] [c85] [c84] [c83] [c82] [c81] [c80] [c79] [c78] [c77] [c76] [c75] [c74] [c73] [c72] [c71] [c70] [c69] [c68] [c67] [c66] [c65] [c64] [c63] [c62] [c61] [c60] [c59] [c57] [c55] [c52] [c51] [c50] [c49] [c48] [c47] [c46] [c45] [c44] [c43] [c42] [c41] [c40] [c39] [c38] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [c29] [c27] [c26] [c25] [c24] [c23] [c21] [c20] [c19] [c18] [c16] [c15] [c14] [c13] [c12] [c11] [c9] [c8] [c7] [c6] [c5] [c4] [c3] [c2] [c1] [i2] [i1]
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