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ORCIDDai Yamamoto
Person information
- affiliation: Fujitsu Laboratories Ltd., Kawasaki, Japan
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Journal Articles
- 2022
[j11]Tadanobu Tsunoda, Kazuaki Nimura, Dai Yamamoto, Kouichi Yasaki, Rikuhiro Kojima, Yosuke Nakamura:
A Chameleon Hash-based Method for Proving Execution of Business Processes. J. Inf. Process. 30: 613-625 (2022)- 2021
- [j10]Rikuhiro Kojima, Dai Yamamoto, Takeshi Shimoyama, Kouichi Yasaki, Kazuaki Nimura:
A New Schnorr Multi-Signatures to Support Both Multiple Messages Signing and Key Aggregation. J. Inf. Process. 29: 525-536 (2021) - [j9]Takanori Machida, Dai Yamamoto, Yuki Unno, Hisashi Kojima:
Novel Deception Techniques for Malware Detection on Industrial Control Systems. J. Inf. Process. 29: 559-571 (2021) - 2016
- [j8]Naoya Torii, Hirotaka Kokubo, Dai Yamamoto, Kouichi Itoh, Masahiko Takenaka, Tsutomu Matsumoto:
ASIC implementation of random number generators using SR latches and its evaluation. EURASIP J. Inf. Secur. 2016: 10 (2016) - [j7]Naoya Torii, Dai Yamamoto, Masahiko Takenaka, Tsutomu Matsumoto:
Experimental Evaluation on the Resistance of Latch PUFs Implemented on ASIC against FIB-Based Invasive Attacks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(1): 118-129 (2016) - 2015
- [j6]Dai Yamamoto, Kazuo Sakiyama, Mitsugu Iwamoto, Kazuo Ohta, Masahiko Takenaka, Kouichi Itoh, Naoya Torii:
A new method for enhancing variety and maintaining reliability of PUF responses and its evaluation on ASICs. J. Cryptogr. Eng. 5(3): 187-199 (2015) - 2013
- [j5]Dai Yamamoto, Kazuo Sakiyama, Mitsugu Iwamoto, Kazuo Ohta, Masahiko Takenaka, Kouichi Itoh:
Variety enhancement of PUF responses using the locations of random outputting RS latches. J. Cryptogr. Eng. 3(4): 197-211 (2013) - 2011
- [j4]Dai Yamamoto, Kouichi Itoh, Jun Yajima
:
Compact Architecture for ASIC and FPGA Implementation of the KASUMI Block Cipher. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2628-2638 (2011) - 2010
- [j3]Dai Yamamoto, Jun Yajima, Kouichi Itoh:
Compact Architecture for ASIC Implementation of the MISTY1 Block Cipher. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(1): 3-12 (2010) - 2009
- [j2]Kouichi Itoh, Dai Yamamoto, Jun Yajima, Wakaha Ogata:
Collision-Based Power Attack for RSA with Small Public Exponent. IEICE Trans. Inf. Syst. 92-D(5): 897-908 (2009) - 2008
- [j1]Dai Yamamoto, Hideki Tode, Toshihiro Masaki, Koso Murakami:
Design and Experimental Evaluation of a Scheme for Maximal Improvement of End-to-End QoS in Heterogeneous IP Networks. IEICE Trans. Commun. 91-B(3): 733-741 (2008)
Conference and Workshop Papers
- 2020
- [c15]Rikuhiro Kojima, Dai Yamamoto, Takeshi Shimoyama, Kouichi Yasaki, Kazuaki Nimura:
A Novel Scheme of Schnorr Multi-signatures for Multiple Messages with Key Aggregation. BWCCA 2020: 284-295 - 2018
- [c14]Takanori Machida, Dai Yamamoto, Ikuya Morikawa, Hirotaka Kokubo, Hisashi Kojima:
A Secure Framework for User-Key Provisioning to SGX Enclaves. NBiS 2018: 725-732 - 2016
- [c13]Naoya Torii, Dai Yamamoto, Tsutomu Matsumoto:
Evaluation of Latch-based Physical Random Number Generator Implementation on 40 nm ASICs. TrustED@CCS 2016: 23-30 - [c12]Naoya Torii, Dai Yamamoto, Tsutomu Matsumoto:
Evaluation of Latch-Based PUFs Implemented on 40 nm ASICs. CANDAR 2016: 642-648 - 2015
- [c11]Takanori Machida, Dai Yamamoto, Mitsugu Iwamoto, Kazuo Sakiyama:
Implementation of double arbiter PUF and its performance evaluation on FPGA. ASP-DAC 2015: 6-7 - 2014
- [c10]Takanori Machida, Dai Yamamoto, Mitsugu Iwamoto, Kazuo Sakiyama:
A New Mode of Operation for Arbiter PUF to Improve Uniqueness on FPGA. FedCSIS 2014: 871-878 - [c9]Dai Yamamoto, Masahiko Takenaka, Kazuo Sakiyama, Naoya Torii:
Security Evaluation of Bistable Ring PUFs on FPGAs using Differential and Linear Analysis. FedCSIS 2014: 911-918 - [c8]Dai Yamamoto, Masahiko Takenaka, Kazuo Sakiyama, Naoya Torii:
A Technique Using PUFs for Protecting Circuit Layout Designs against Reverse Engineering. IWSEC 2014: 158-173 - 2013
- [c7]Hirotaka Kokubo, Dai Yamamoto, Masahiko Takenaka, Kouichi Itoh, Naoya Torii:
Evaluation of ASIC Implementation of Physical Random Number Generators Using RS Latches. CARDIS 2013: 3-15 - 2012
- [c6]Dai Yamamoto, Gabriel Hospodar, Roel Maes, Ingrid Verbauwhede:
Performance and Security Evaluation of AES S-Box-Based Glitch PUFs on FPGAs. SPACE 2012: 45-62 - 2011
- [c5]Dai Yamamoto, Kazuo Sakiyama, Mitsugu Iwamoto, Kazuo Ohta, Takao Ochiai, Masahiko Takenaka, Kouichi Itoh:
Uniqueness Enhancement of PUF Responses Based on the Locations of Random Outputting RS Latches. CHES 2011: 390-406 - 2010
- [c4]Dai Yamamoto, Kouichi Itoh, Jun Yajima:
A Very Compact Hardware Implementation of the KASUMI Block Cipher. WISTP 2010: 293-307 - 2008
- [c3]Dai Yamamoto, Jun Yajima, Kouichi Itoh:
A Very Compact Hardware Implementation of the MISTY1 Block Cipher. CHES 2008: 315-330 - 2007
- [c2]Dai Yamamoto, Hideki Tode, Toshihiro Masaki, Koso Murakami:
Design and Empirical Evaluation of Control Scheme for End-to-End Delay Stabilization and Packet Loss Improvement in Broadband IP Network. ICCCN 2007: 549-555 - 2005
- [c1]Dai Yamamoto, Rie Fujita, Hideki Tode, Koso Murakami, Toshihiro Masaki:
A Method for Guaranteeing End-to-End Delay by Mutual Cooperation between IP Routers. LCN 2005: 511-512
Informal and Other Publications
- 2020
- [i2]Takanori Machida, Dai Yamamoto, Yuki Unno, Hisashi Kojima:
Novel Deception Techniques for Malware Detection on Industrial Control Systems. IACR Cryptol. ePrint Arch. 2020: 255 (2020) - 2014
- [i1]Naoya Torii, Dai Yamamoto, Masahiko Takenaka, Tsutomu Matsumoto:
Dynamic Behavior of RS latches using FIB processing and probe connection. IACR Cryptol. ePrint Arch. 2014: 870 (2014)
Coauthor Index
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