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Sivaprakasam Suresh
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Journal Articles
- 2007
- [j1]Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti:
A novel approach to the placement and routing problems for field programmable gate arrays. Appl. Soft Comput. 7(1): 455-470 (2007)
Conference and Workshop Papers
- 2007
- [c9]Krishnan Ramakrishnan, R. Rajaraman, Sivaprakasam Suresh, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin:
Variation Impact on SER of Combinational Circuits. ISQED 2007: 911-916 - [c8]Krishnan Ramakrishnan, Sivaprakasam Suresh, Narayanan Vijaykrishnan, Mary Jane Irwin:
Impact of NBTI on FPGAs. VLSI Design 2007: 717-722 - 2004
- [c7]Permandla Pratibha, Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti:
An Evolutionary Algorithm for Automatic Spatial Partitioning in Reconfigurable Environments. MICAI 2004: 735-745 - 2003
- [c6]Permandla Pratibha, Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti:
An enhanced evolutionary approach to spatial partitioning for reconfigurable environments. IEEE Congress on Evolutionary Computation 2003: 1708-1715 - [c5]Permandla Pratibha, Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Ganesh, V. Kamakoti:
A Parallel Evolutionary Approach to Spatial Partitioning in Reconfigurable Environments. IICAI 2003: 938-951 - [c4]Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti:
A Parallel Genetic Approach to the Placement Problem for Field Programmable Gate Arrays. IPDPS 2003: 184 - [c3]L. Kalyan Kumar, Aditya S. Ramani, Amol J. Mupid, V. Kamakoti, Sivaprakasam Suresh:
On-Line Location of Multiple Faults in LUT Based Reconfigurable Systems. VLSI 2003: 224-232 - 2002
- [c2]Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti:
A novel three phase parallel genetic approach to routing for field programmable gate arrays. FPT 2002: 336-339 - 1994
- [c1]Sreejit Chakravarty, Sivaprakasam Suresh:
IDDQ Measurement Based Diagnosis of Bridging Faults in Full Scan Circuits. VLSI Design 1994: 179-182
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