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ORCIDFang Zhou 0001
Person information
- affiliation: University of Aeronautics and Astronautics, College of Electronic and Information Engineering Nanjing, China
Other persons with the same name
- Fang Zhou — disambiguation page
- Fang Zhou 0002 — University of Helsinki, Finland
- Fang Zhou 0003 — Florida Atlantic University, Boca Raton, USA
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Journal Articles
- 2021
[j16]Fang Zhou, Caixian Fei, Ning Wu, Fen Ge:
Highly efficient architecture of elliptic curve scalar multiplication with fault tolerance over GF(2m). IEICE Electron. Express 18(11): 20210160 (2021)- 2020
- [j15]Lei Zhang
, Ning Wu, Fen Ge, Fang Zhou, Mahammad Rehan Yahya:
A Dynamic Branch Predictor Based on Parallel Structure of SRNN. IEEE Access 8: 86230-86237 (2020) - 2019
- [j14]Qiangjia Bi, Ning Wu, Fang Zhou, Jinbao Zhang, Muhammad Rehan Yahya, Fen Ge:
Fault attack hardware Trojan detection method based on ring oscillator. IEICE Electron. Express 16(8): 20190143 (2019) - [j13]Fang Zhou, Ning Wu, Xiaoqiang Zhang, Jinbao Zhang:
A new method for resisting collision attack based on parallel random delay S-box. IEICE Electron. Express 16(11): 20190192 (2019) - [j12]Jinbao Zhang, Ning Wu, Jianhua Li, Fang Zhou:
A novel differential fault analysis using two-byte fault model on AES Key schedule. IET Circuits Devices Syst. 13(5): 661-666 (2019) - 2018
- [j11]Jinbao Zhang, Ning Wu, Fen Ge, Fang Zhou, Xiaoqing Zhang:
Countermeasure against fault sensitivity analysis based on clock check block. IEICE Electron. Express 15(11): 20180433 (2018) - [j10]Yong Zhang, Ning Wu, Fang Zhou, Xiaoqiang Zhang, Jinbao Zhang:
High performance AES-GCM implementation based on efficient AES and FR-KOA multiplier. IEICE Electron. Express 15(14): 20180559 (2018) - [j9]Yunfei Ye, Ning Wu, Xiaoqiang Zhang, Liling Dong, Fang Zhou:
An Optimized Design for Compact Masked AES S-Box Based on Composite Field and Common Subexpression Elimination Algorithm. J. Circuits Syst. Comput. 27(11): 1850171:1-1850171:11 (2018) - 2017
- [j8]Gaizhen Yan, Ning Wu, Fen Ge, Hao Xiao, Fang Zhou:
ArR-DTM: A routing-based DTM for 3D NoCs by adaptive degree regulation. IEICE Electron. Express 14(9): 20170203 (2017) - [j7]Yaoping Liu, Ning Wu, Xiaoqiang Zhang, Fang Zhou:
A new compact hardware architecture of S-Box for block ciphers AES and SM4. IEICE Electron. Express 14(11): 20170358 (2017) - [j6]Gaizhen Yan, Ning Wu, Fen Ge, Hao Xiao, Fang Zhou:
Collaborative fuzzy-based partially-throttling dynamic thermal management scheme for three-dimensional networks-on-chip. IET Comput. Digit. Tech. 11(1): 24-32 (2017) - 2016
- [j5]Xiaoqiang Zhang, Ning Wu, Fang Zhou, Jianhua Li, Yasir Khizar:
Low-delay parallel Chien search architecture for RS decoder. IEICE Electron. Express 13(19): 20160729 (2016) - [j4]Jinbao Zhang, Ning Wu, Xiaoqiang Zhang, Fang Zhou:
Against fault attacks based on random infection mechanism. IEICE Electron. Express 13(21): 20160872 (2016) - [j3]Xiaoqiang Zhang, Ning Wu, Fang Zhou, Fen Ge:
Optimization of Area and Delay for Implementation of the Composite Field Advanced Encryption Standard S-Box. J. Circuits Syst. Comput. 25(5): 1650037:1-1650037:29 (2016) - 2015
- [j2]Taotao Zhang, Ning Wu, Lei Zhou, Fang Zhou:
BTorus: A novel thermal-traffic balanced NoC topology. IEICE Electron. Express 12(8): 20150234 (2015) - 2014
- [j1]Xiaoqiang Zhang, Ning Wu, Fang Zhou, Xin Chen:
An optimized delay-aware common subexpression elimination algorithm for hardware implementation of binary-field linear transform. IEICE Electron. Express 11(22): 20140934 (2014)
Conference and Workshop Papers
- 2023
- [c21]Wenqiang Gong, Fang Zhou, Fen Ge:
A Multi-mode Convolution Coprocessor Based on RISC-V Instruction Set Architecture. ASICON 2023: 1-5 - [c20]Jiantao Ye, Fen Ge, Fang Zhou:
A Method of Mapping Convolutional Neural Networks on Resource-limited NoC Platform. ASICON 2023: 1-4 - [c19]Guohui Zhang, Fen Ge, Fang Zhou:
A Deep Q Network Hardware Accelerator Based on Heterogeneous Computing. ASICON 2023: 1-4 - [c18]Jin Zhao, Fang Zhou, Fen Ge, Shuning Wu, Hao Wang:
A Lightweight BiSeNet Embedded with YOLOv5 Feature Fusion Network. ICCT 2023: 608-612 - 2022
- [c17]Kaiyu Zhao, Fang Zhou, Ning Wu, Jin Zhao, Fen Ge:
The Design of a Novel Hardware Trojan without Inactive Signal for AES. ICCT 2022: 1159-1163 - [c16]Zhixiang Xu, Ning Wu, Fang Zhou, Fen Ge:
A Defense Method Against Persistent Fault Attack. ICCT 2022: 1323-1327 - [c15]Ziyu Li, Fen Ge, Fang Zhou, Ning Wu:
An A3C Deep Reinforcement Learning FPGA Accelerator based on Heterogeneous Compute Units. ICCT 2022: 1521-1525 - [c14]Xinyu Wang, Ning Wu, Fang Zhou, Fen Ge:
Efficient Configurable Digit-Serial Multiplier Based on Improved Karatsuba Algorithm over GF(2m). ICCT 2022: 1531-1535 - [c13]Xin Yue, Fen Ge, Fang Zhou, Ning Wu, Yi Zhang:
A Hybrid CNN Compression Approach for Hardware Acceleration. ICCT 2022: 1546-1550 - [c12]Wang Han, Ning Wu, Fang Zhou, Fen Ge:
Reconfigurable Multi-algorithm Neural Network Accelerator Based on Target Detection. ICCT 2022: 1555-1559 - 2021
- [c11]Jin Wen, Ning Wu, Fen Ge, Fang Zhou, Zhixiang Xu, Benjun Zhang:
An Anti-DPA Elliptic Curve Cryptography Scalar Multiplier with Randomized Base Point. ICCT 2021: 100-104 - [c10]Tong Lu, Fang Zhou, Ning Wu, Fen Ge, Benjun Zhang:
Hardware Trojan Detection Method for Gate-Level Netlists Based on the Idea of Few-Shot Learning. ICCT 2021: 301-305 - [c9]Chenchen Cui, Fen Ge, Ziyu Li, Xin Yue, Fang Zhou, Ning Wu:
Design and Implementation of OpenCL-Based FPGA Accelerator for YOLOv2. ICCT 2021: 1004-1007 - [c8]Ying Yang, Fen Ge, Danfeng Qiu, Xin Yue, Ziyu Li, Fang Zhou, Ning Wu:
Implementation of Reconfigurable CNN-LSTM Accelerator Based on FPGA. ICCT 2021: 1026-1030 - 2020
- [c7]Liangkai Zhao, Ning Wu, Fen Ge, Fang Zhou, Jiahui Zhang, Tong Lu:
Small Area Configurable Deep Neural Network Accelerator for IoT System. ICCT 2020: 795-799 - [c6]Yayue Zhao, Fen Ge, Chenchen Cui, Fang Zhou, Ning Wu:
A Mapping Method for Convolutional Neural Networks on Network-on-Chip. ICCT 2020: 916-920 - [c5]Liang Han, Ning Wu, Fen Ge, Fang Zhou, Jin Wen, Peiyao Qing:
Differential Fault Attack for the Iterative Operation of AES-192 Key Expansion. ICCT 2020: 1156-1160 - [c4]Caixian Fei, Fang Zhou, Ning Wu, Fen Ge, Jin Wen, Peiyao Qin:
A Scalable Bit-Parallel Word-Serial Multiplier with Fault Detection on GF(2^m). ICCT 2020: 1660-1664 - [c3]Weifeng Zhang, Fen Ge, Chenchen Cui, Ying Yang, Fang Zhou, Ning Wu:
Design and Implementation of LSTM Accelerator Based on FPGA. ICCT 2020: 1675-1679 - 2019
- [c2]Xiangli Li, Fen Ge, Ben Rui, Ning Wu, Fang Zhou:
A dual-threshold credit-based flow control mechanism for 3D Network-on-Chip. ICICDT 2019: 1-4 - [c1]Xiao Yu, Ning Wu, Fang Zhou, Jinbao Zhang, Xinggan Zhang:
A Compact Hardware Implementation for the SCA-resistant PRESENT Cipher. IECON 2019: 5463-5468
Coauthor Index
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