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2010 – 2019
- 2018
[j8]Carlos Briseno-Vidrios
, Dadian Zhou, Suraj Prakash, Qiyuan Liu, Alexander Edward, Eric G. Soenen, Martin Kinyua, José Silva-Martínez:
A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs. IEEE J. Solid State Circuits 53(11): 3280-3292 (2018)- [j7]Qiyuan Liu, Alexander Edward, Dadian Zhou, José Silva-Martínez:
A Continuous-Time MASH 1-1-1 Delta-Sigma Modulator With FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 26(4): 756-767 (2018) - 2017
- [j6]Alexander Edward, Qiyuan Liu, Carlos Briseno-Vidrios, Martin Kinyua, Eric G. Soenen, Aydin Ilker Karsilayan, José Silva-Martínez:
A 43-mW MASH 2-2 CT ΣΔ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS. IEEE J. Solid State Circuits 52(2): 448-459 (2017) - [j5]Carlos Briseno-Vidrios, Alexander Edward, Ayman Shafik, Samuel Palermo, José Silva-Martínez:
A 75-MHz Continuous-Time Sigma-Delta Modulator Employing a Broadband Low-Power Highly Efficient Common-Gate Summing Stage. IEEE J. Solid State Circuits 52(3): 657-668 (2017) - [j4]Qiyuan Liu, Alexander Edward, Martin Kinyua, Eric G. Soenen, José Silva-Martínez:
A Low-Power Digitizer for Back-Illuminated 3-D-Stacked CMOS Image Sensor Readout With Passing Window and Double Auto-Zeroing Techniques. IEEE J. Solid State Circuits 52(6): 1591-1604 (2017) - [c3]Carlos Briseno-Vidrios, Dadian Zhou, Suraj Prakash, Qiyuan Liu, Alexander Edward, José Silva-Martínez:
A 13bit 200MS/S pipeline ADC with current-mode MDACs. ISCAS 2017: 1-4 - [c2]Qiyuan Liu, Alexander Edward, Carlos Briseno-Vidrios, Negar Rashidi, José Silva-Martínez:
High-performance continuous-time MASH sigma-delta ADCs for broadband wireless applications. MWSCAS 2017: 297-300 - 2016
- [j3]Carlos Briseno-Vidrios, Alexander Edward, Negar Rashidi, José Silva-Martínez:
A 4 Bit Continuous-Time ΣΔ Modulator With Fully Digital Quantization Noise Reduction Algorithm Employing a 7 Bit Quantizer. IEEE J. Solid State Circuits 51(6): 1398-1409 (2016) - 2015
- [c1]Carlos Briseno-Vidrios, Alexander Edward, Ayman Shafik, Samuel Palermo, José Silva-Martínez:
A 75 MHz BW 68dB DR CT-ΣΔ modulator with single amplifier biquad filter and a broadband low-power common-gate summing technique. VLSIC 2015: 254- - 2014
- [j2]Alexander Edward, José Silva-Martínez:
General Analysis of Feedback DAC's Clock Jitter in Continuous-Time Sigma-Delta Modulators. IEEE Trans. Circuits Syst. II Express Briefs 61-II(7): 506-510 (2014) - 2012
- [j1]Alexander Edward, Pak Kwong Chan:
An Ultra-Low Voltage Analog Front End for Strain Gauge Sensory System Application in 0.18 µm CMOS. IEICE Trans. Electron. 95-C(4): 733-743 (2012)
Coauthor Index
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