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Ioannis Tsatsaragkos
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2010 – 2019
- 2018
- [j2]Ioannis Tsatsaragkos, Vassilis Paliouras:
A Reconfigurable LDPC Decoder Optimized for 802.11n/ac Applications. IEEE Trans. Very Large Scale Integr. Syst. 26(1): 182-195 (2018) - 2015
- [j1]Ioannis Tsatsaragkos, Vassilis Paliouras:
Approximate Algorithms for Identifying Minima on Min-Sum LDPC Decoders and Their Hardware Implementation. IEEE Trans. Circuits Syst. II Express Briefs 62-II(8): 766-770 (2015) - 2012
- [c8]Ahmed Mahdi, Panagiotis Sakellariou, Nikos Kanistras, Ioannis Tsatsaragkos, Vassilis Paliouras:
Hardware design and verification techniques for Giga-bit Forward-Error Correction systems on FPGAs. ICECS 2012: 89-92 - [c7]Panagiotis Sakellariou, Ioannis Tsatsaragkos, Nikos Kanistras, Ahmed Mahdi, Vassilis Paliouras:
An FPGA-based prototyping method for verification, characterization and optimization of LDPC error correction systems. ICSAMOS 2012: 286-293 - [c6]G. Spourlis, Ioannis Tsatsaragkos, Nikos Kanistras, Vassilis Paliouras:
Error Floor Compensation for LDPC Codes Using Concatenated Schemes. SiPS 2012: 155-160 - [c5]Nikos Kanistras, Ioannis Tsatsaragkos, Vassilis Paliouras:
Propagation of LLR Saturation and Quantization Error in LDPC Min-Sum Iterative Decoding. SiPS 2012: 276-281 - 2011
- [c4]Ioannis Tsatsaragkos, Nikos Kanistras, Vassilis Paliouras:
A syndrome-based LDPC decoder with very low error floor. DSP 2011: 1-6 - [c3]Ioannis Tsatsaragkos, Nikos Kanistras, Vassilis Paliouras:
Multiple LDPC decoder of very low bit-error rate. DSP 2011: 1-6 - [c2]Nikos Kanistras, Ioannis Tsatsaragkos, Ahmed Mahdi, Konstantina Karagianni, Vassilis Paliouras, Fotios Gioulekas, E. Lalos, Kostas Adaos, Michael K. Birbas, Panos Karaivazoglou, M. V. Koziotis, M. Perakis:
Digital baseband challenges for a 60GHz gigabit link. ICECS 2011: 346-349 - [c1]Ioannis Tsatsaragkos, Vassilis Paliouras:
A flexible layered LDPC decoder. ISWCS 2011: 36-40
Coauthor Index
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