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ORCIDAlp Arslan Bayrakci
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2020 – today
- 2024
[j5]Gizem Sungu Terci
, Enes Abdulhalik, Alp Arslan Bayrakci, Betul Boz:
BitEA: BitVertex Evolutionary Algorithm to Enhance Performance for Register Allocation. IEEE Access 12: 115497-115514 (2024)- 2023
- [j4]Fatma Nur Esirci, Alp Arslan Bayrakci:
Delay based hardware Trojan detection exploiting spatial correlations to suppress variations. Integr. 91: 107-118 (2023)
2010 – 2019
- 2019
- [c4]Fatma Nur Esirci, Alp Arslan Bayrakci:
Acceleration of Spatial Correlation Based Hardware Trojan Detection Using Shared Grids Ratio. MACIS 2019: 187-201 - 2017
- [c3]Fatma Nur Esirci, Alp Arslan Bayrakci:
Hardware Trojan detection based on correlated path delays in defiance of variations with spatial correlations. DATE 2017: 163-168 - 2016
- [j3]Alp Arslan Bayrakci:
Accelerated Accurate Timing Yield Estimation Based on Control Variates and Importance Sampling. IEEE Trans. Very Large Scale Integr. Syst. 24(8): 2787-2798 (2016) - 2015
- [j2]Alp Arslan Bayrakci:
Stochastic logical effort as a variation aware delay model to estimate timing yield. Integr. 48: 101-108 (2015) - 2013
- [c2]Alp Arslan Bayrakci:
On the accuracy of Monte Carlo yield estimators. VLSI-SoC 2013: 56-57 - 2010
- [b1]Alp Arslan Bayrakci:
Fast and accurate statistical timing analysis of digital circuits for timing yield estimation based on transistor level simulations (Transistör düzeyi simülasyonlara dayanan zamanlama verimi tahmini için sayısal devrelerin hızlı ve doğru istatiksel zamanlama analizi). Koç University, Turkey, 2010 - [j1]Alp Arslan Bayrakci, Alper Demir, Serdar Tasiran:
Fast Monte Carlo Estimation of Timing Yield With Importance Sampling and Transistor-Level Circuit Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(9): 1328-1341 (2010)
2000 – 2009
- 2008
- [i1]Alp Arslan Bayrakci, Alper Demir, Serdar Tasiran:
Fast Monte Carlo Estimation of Timing Yield: Importance Sampling with Stochastic Logical Effort (ISLE). CoRR abs/0805.2627 (2008) - 2007
- [c1]Alp Arslan Bayrakci, Ahmet Akkas:
Reduced Delay BCD Adder. ASAP 2007: 266-271
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