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2020 – today
- 2023
[c18]Boma A. Adhi, Carlos Cortes, Emanuele Del Sozzo
, Tomohiro Ueno, Yiyu Tan, Takuya Kojima, Artur Podobas, Kentaro Sano:
Less for More: Reducing Intra-CGRA Connectivity for Higher Performance and Efficiency in HPC. IPDPS Workshops 2023: 452-459- 2022
- [c17]Boma A. Adhi, Carlos Cortes, Yiyu Tan, Takuya Kojima, Artur Podobas, Kentaro Sano:
The Cost of Flexibility: Embedded versus Discrete Routers in CGRAs for HPC. CLUSTER 2022: 347-356 - [c16]Boma A. Adhi, Carlos Cortes, Tomohiro Ueno, Yiyu Tan, Takuya Kojima, Artur Podobas, Kentaro Sano:
Exploring Inter-tile Connectivity for HPC-oriented CGRA with Lower Resource Usage. FPT 2022: 1-4 - [c15]Takuya Kojima, Boma A. Adhi, Carlos Cortes, Yiyu Tan, Kentaro Sano:
An Architecture- Independent CGRA Compiler enabling OpenMP Applications. IPDPS Workshops 2022: 631-638 - [c14]Boma A. Adhi, Carlos Cortes, Yiyu Tan, Takuya Kojima, Artur Podobas, Kentaro Sano:
Exploration Framework for Synthesizable CGRAs Targeting HPC: Initial Design and Evaluation. IPDPS Workshops 2022: 639-646 - 2020
- [c13]Yiyu Tan, Toshiyuki Imamura:
An FPGA-based Sound Field Rendering System. CLUSTER 2020: 414-415 - [i1]Roman Iakymchuk, Daichi Mukunoki, Artur Podobas, Fabienne Jézéquel, Toshiyuki Imamura, Norihisa Fujita, Jens Huthmann, Shuhei Kudo, Yiyu Tan, Jens Domke, Kai Torben Ohlhus, Takeshi Fukaya, Takeo Hoshi, Yuki Murakami, Maho Nakata, Takeshi Ogita, Kentaro Sano, Taisuke Boku:
White Paper from Workshop on Large-scale Parallel Numerical Computing Technology (LSPANC 2020): HPC and Computer Arithmetic toward Minimal-Precision Computing. CoRR abs/2004.04628 (2020)
2010 – 2019
- 2019
- [c12]Yiyu Tan, Toshiyuki Imamura, Daichi Mukunoki:
Design of an FPGA-Based Matrix Multiplier with Task Parallelism. PARCO 2019: 241-250 - 2018
- [c11]Yiyu Tan, Toshiyuki Imamura:
Performance Evaluation of a Toolkit for Sparse Tensor Decomposition. HPDC (Posters/Doctoral Consortium) 2018: 5-6 - 2017
- [c10]Yiyu Tan, Toshiyuki Imamura:
An energy-efficient FPGA-based matrix multiplier. ICECS 2017: 514-517
2000 – 2009
- 2009
- [j2]Yiyu Tan, Chihang Yau, Anthony S. Fong, Xiaojian Yang:
An instruction folding solution for a Java processor. Comput. Syst. Sci. Eng. 24(3) (2009) - [c9]Yiyu Tan, Chihang Yau, Anthony S. Fong:
A Object Model for Java and Its Architectural Support. ITNG 2009: 831-836 - 2008
- [c8]Chihang Yau, Yiyu Tan, Anthony Shi-Sheung Fong, Pak Lun Mok:
An Extensive Hardware/Software Co-design on a Descriptor-Based Embedded Java Processor. ICYCS 2008: 142-147 - 2007
- [c7]Yiyu Tan, Anthony S. Fong, Xiaojian Yang:
Architectural Solution to Object-Oriented Programming. Asia-Pacific Computer Systems Architecture Conference 2007: 387-398 - [c6]Yiyu Tan, Anthony S. Fong, Xiaojian Yang:
An Instruction Folding Solution to a Java Processor. NPC 2007: 415-424 - 2006
- [j1]Yiyu Tan, Lo Wan Yiu, Chihang Yau, Richard Li, Anthony S. Fong:
A Java processor with hardware-support object-oriented instructions. Microprocess. Microsystems 30(8): 469-479 (2006) - [c5]Yiyu Tan, Chihang Yau, Anthony S. Fong:
Architectural Support on Object-Oriented Programming in a JAVA Processor. ASAP 2006: 303-310 - 2005
- [c4]Chihang Yau, Yiyu Tan, Anthony S. Fong:
A Novel Just-In-Time Compiler on an Embedded Object-Oriented Processor. CIT 2005: 771-775 - [c3]Chihang Yau, Yiyu Tan, Anthony S. Fong, Wing Shing Yu:
Hardware Concurrent Garbage Collection for Short-Lived Objects in Mobile Java Devices. EUC 2005: 47-56 - [c2]Chihang Yau, Yiyu Tan, Pak Lun Mok, Wing Shing Yu, Anthony S. Fong:
A Hardware/Software Co-design and Co-verification on a Novel Embedded Object-Oriented Processor. EUC 2005: 371-380 - [c1]Yiyu Tan, Chihang Yau, Kaiman Lo, Pak Lun Mok, Anthony S. Fong:
A Novel JAVA Processor for Embedded Devices. SAMOS 2005: 112-121
Coauthor Index
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