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Hsuan-Ming Chou
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2010 – 2019
- 2016
- [j2]Hsuan-Ming Chou, Yi-Chiao Chen, Keng-Hao Yang, Jean Tsao, Shih-Chieh Chang, Wen-Ben Jone, Tien-Fu Chen:
High-Performance Deadlock-Free ID Assignment for Advanced Interconnect Protocols. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 1169-1173 (2016) - 2015
- [j1]Hsuan-Ming Chou, Ming-Yi Hsiao, Yi-Chiao Chen, Keng-Hao Yang, Jean Tsao, Chiao-Ling Lung, Shih-Chieh Chang, Wen-Ben Jone, Tien-Fu Chen:
Soft-Error-Tolerant Design Methodology for Balancing Performance, Power, and Reliability. IEEE Trans. Very Large Scale Integr. Syst. 23(9): 1628-1639 (2015) - [c7]Hsuan-Ming Chou, Hong-Chang Wu, Yi-Chiao Chen, Jean Tsao, Shih-Chieh Chang:
Hybrid coverage assertions for efficient coverage analysis across simulation and emulation environments. ASP-DAC 2015: 594-599 - 2014
- [c6]Hsuan-Ming Chou, Hong-Chang Wu, Yi-Chiao Chen, Shih-Chieh Chang:
Concurrency-oriented SoC re-certification by reusing block-level test vectors. ISQED 2014: 140-147 - 2012
- [c5]Mac Y. C. Kao, Kun-Ting Tsai, Hsuan-Ming Chou, Shih-Chieh Chang:
Post silicon skew tuning: Survey and analysis. ASP-DAC 2012: 646-651 - [c4]Hsiu-Yi Lin, Chun-Yao Wang, Shih-Chieh Chang, Yung-Chih Chen, Hsuan-Ming Chou, Ching-Yi Huang, Yen-Chi Yang, Chun-Chien Shen:
A probabilistic analysis method for functional qualification under Mutation Analysis. DATE 2012: 147-152 - 2011
- [c3]Hsuan-Ming Chou, Hao Yu, Shih-Chieh Chang:
Useful-skew clock optimization for multi-power mode designs. ICCAD 2011: 647-650 - 2010
- [c2]Yu-Chien Kao, Hsuan-Ming Chou, Kun-Ting Tsai, Shih-Chieh Chang:
An efficient phase detector connection structure for the skew synchronization system. DAC 2010: 729-734 - [c1]Yu-Chien Kao, Hsuan-Ming Chou, Kun-Ting Tsai, Shih-Chieh Chang:
Synthesis of an efficient controlling structure for post-silicon clock skew minimization. ICCAD 2010: 746-749
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