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Books and Theses
- 2001
[b1]Ulrich Nageldinger:
Coarse-grained reconfigurable architecture design space exploration. Kaiserslautern University of Technology, Germany, 2001, ISBN 978-3-925178-65-8, pp. I-XVI, 1-277
Conference and Workshop Papers
- 2008
- [c24]Andreas W. Liehr, Klaus J. Buchenrieder
, Heike S. Rolfs, Ulrich Nageldinger:
Generation of MARTE Allocation Models from Activity Threads. FDL (Selected Papers) 2008: 43-56 - [c23]Andreas W. Liehr, Heike S. Rolfs, Klaus Buchenrieder, Ulrich Nageldinger:
Generating MARTE Allocation Models from Activity Threads. FDL 2008: 215-220 - [c22]Jochen Zimmermann, Oliver Bringmann, Joachim Gerlach, Florian Schaefer, Ulrich Nageldinger:
Comprehensive Platform and Component Modeling of Heterogeneous Interconnected Systems (invited). FDL 2008: 227-232 - 2005
- [c21]Robert Fischer, Klaus Buchenrieder, Ulrich Nageldinger:
Reducing the Power Consumption of FPGAs through Retiming. ECBS 2005: 89-94 - [c20]Maik Boden, Alex Gleich, Steffen Rülke, Ulrich Nageldinger:
A Low-Cost Realization of an Adaptable Protocol Processing Unit. IPDPS 2005 - 2002
- [c19]Klaus Buchenrieder, Ulrich Nageldinger, Andreas Pyttel, Alexander Sedlmeier:
Integration of Reconfigurable Hardware into System-Level Design. FPL 2002: 987-996 - [c18]Klaus Buchenrieder, Ulrich Nageldinger, Andreas Pyttel, Alexander Sedlmeier:
System Prototyping by Integration of Reconfigurable Hardware into a Heterogeneous System Model. IEEE International Workshop on Rapid System Prototyping 2002: 115-121 - 2000
- [c17]Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger:
KressArray Xplorer: a new CAD environment to optimize reconfigurable datapath array. ASP-DAC 2000: 163-168 - [c16]Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger:
Synthesis and domain-specific optimization of KressArray-based reconfigurable computing engines (poster abstract). FPGA 2000: 222 - [c15]Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger:
Generation of Design Suggestions for Coarse-Grain Reconfigurable Architectures. FPL 2000: 389-399 - [c14]Reiner W. Hartenstein, Thomas Hoffmann, Ulrich Nageldinger:
Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures. PATMOS 2000: 118-128 - 1999
- [c13]Reiner W. Hartenstein, Michael Herz, Ulrich Nageldinger, Thomas Hoffmann:
An Internet Based Development Framework for Reconfigurable Computing. FPL 1999: 155-164 - [c12]Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger:
Mapping Applications onto Reconfigurable Kress Arrays. FPL 1999: 385-390 - [c11]Michael Herz, Thomas Hoffmann, Ulrich Nageldinger, Christian Schreiber:
XMDS: The Xputer Multimedia Development System. HICSS 1999 - [c10]Michael Herz, Thomas Hoffmann, Ulrich Nageldinger, Christian Schreiber:
Interfacing the MoM-PDA to an Internet-based Development System. HICSS 1999 - 1998
- [c9]Jürgen Becker, Reiner W. Hartenstein, Michael Herz, Ulrich Nageldinger:
Parallelization in Co-Compilation for Configurable Accelerators. ASP-DAC 1998: 23-33 - [c8]Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger:
Exploiting Contemporary Memory Techniques in Reconfigurable Accelerators. FPL 1998: 189-198 - [c7]Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger:
On Reconfigurable Co-processing Units. IPPS/SPDP Workshops 1998: 67-72 - 1997
- [c6]Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger:
A Novel Universal Sequencer Hardware. ARCS 1997: 143-152 - [c5]Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger:
A Novel Sequencer Hardware for Application Specific Computing. ASAP 1997: 392-401 - [c4]Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger:
Data scheduling to increase performance of parallel accelerators. FPL 1997: 294-303 - [c3]Rainer Kress, Reiner W. Hartenstein, Ulrich Nageldinger:
An operating system for custom computing machines based on the Xputer paradigm. FPL 1997: 304-313 - 1996
- [c2]Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger:
A Synthesis System For Bus-Based Wavefront Array Architectures. ASAP 1996: 274-283 - [c1]Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger:
A Partitioning Programming Environment for a Novel Parallel Architecture. IPPS 1996: 544-548
Coauthor Index
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