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Gerald R. Morris
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Journal Articles
- 2013
- [j7]Gerald R. Morris, Khalid H. Abed:
Mapping Floating-Point Kernels onto High Performance Reconfigurable Computers. J. Comput. 8(4): 859-873 (2013) - [j6]Khalid H. Abed, Gerald R. Morris:
Improving performance of codes with large/irregular stride memory access patterns via high performance reconfigurable computers. J. Parallel Distributed Comput. 73(11): 1430-1438 (2013) - [j5]Gerald R. Morris, Khalid H. Abed:
Mapping a Jacobi Iterative Solver onto a High-Performance Heterogeneous Computer. IEEE Trans. Parallel Distributed Syst. 24(1): 85-91 (2013) - 2009
- [j4]Justin L. Rice, Khalid H. Abed, Gerald R. Morris:
Design Heuristics for Mapping Floating-Point Scientific Computational Kernels onto High Performance Reconfigurable Computers. J. Comput. 4(6): 542-553 (2009) - 2008
- [j3]Gerald R. Morris, Viktor K. Prasanna:
A pipelined-loop-compatible architecture and algorithm to reduce variable-length sets of floating-point data on a reconfigurable computer. J. Parallel Distributed Comput. 68(7): 913-921 (2008) - 2007
- [j2]Gerald R. Morris, Viktor K. Prasanna:
Sparse Matrix Computations on Reconfigurable Hardware. Computer 40(3): 58-64 (2007) - [j1]Ling Zhuo, Gerald R. Morris, Viktor K. Prasanna:
High-Performance Reduction Circuits Using Deeply Pipelined Operators on FPGAs. IEEE Trans. Parallel Distributed Syst. 18(10): 1377-1392 (2007)
Conference and Workshop Papers
- 2006
- [c5]Gerald R. Morris, Viktor K. Prasanna, Richard D. Anderson:
An FPGA-Based Application-Specific Processor for Efficient Reduction of Multiple Variable-Length Floating-Point Data Sets. ASAP 2006: 323-330 - [c4]Gerald R. Morris, Viktor K. Prasanna, Richard D. Anderson:
A Hybrid Approach for Mapping Conjugate Gradient onto an FPGA-Augmented Reconfigurable Supercomputer. FCCM 2006: 3-12 - 2005
- [c3]Gerald R. Morris, Ling Zhuo, Viktor K. Prasanna:
High-Performance FPGA-Based General Reduction Methods. FCCM 2005: 323-324 - [c2]Ling Zhuo, Gerald R. Morris, Viktor K. Prasanna:
Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores. IPDPS 2005 - [c1]Gerald R. Morris, Viktor K. Prasanna:
An FPGA-Based Floating-Point Jacobi Iterative Solver. ISPAN 2005: 420-427
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