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2020 – today
- 2020
[j64]Qingli Guo
, Jing Ye, Yu Hu, Guohe Zhang, Xiaowei Li, Huawei Li:
MultiPAD: A Multivariant Partition-Based Method for Audio Adversarial Examples Detection. IEEE Access 8: 63368-63380 (2020)- [j63]Huina Chao, Huawei Li, Xiaoyu Song, Tiancheng Wang, Xiaowei Li:
Evaluating and Constraining Hardware Assertions with Absent Scenarios. J. Comput. Sci. Technol. 35(5): 1198-1216 (2020) - [j62]Hui Li, Huawei Li, Yanjie Lv, Yongjun Wang, Zongshuai Wang, Caiyun Xin, Shengqun Liu, Xiancan Zhu, Fengbin Song, Xiangnan Li:
Salt Priming Protects Photosynthetic Electron Transport against Low-Temperature-Induced Damage in Wheat. Sensors 20(1): 62 (2020) - [j61]Liyang Lai, Kun-Han Tsai, Huawei Li:
GPGPU-Based ATPG System: Myth or Reality? IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(1): 239-247 (2020) - [j60]Ying Zhang, Krishnendu Chakrabarty, Zebo Peng, Ahmed Rezine, Huawei Li, Petru Eles, Jianhui Jiang:
Software-Based Self-Testing Using Bounded Model Checking for Out-of-Order Superscalar Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(3): 714-727 (2020) - [j59]Hang Lu, Mingzhe Zhang, Yinhe Han, Qi Wang, Huawei Li, Xiaowei Li:
Architecting Effectual Computation for Machine Learning Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2654-2667 (2020) - [j58]Aijiao Cui, Mengyang Li, Gang Qu, Huawei Li:
A Guaranteed Secure Scan Design Based on Test Data Obfuscation by Cryptographic Hash. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 4524-4536 (2020) - [j57]Mengyun Zhou, Lizhe Wang, Xiaoyu Chen, Si Wu, Huawei Li:
Tile-based polygon overlay of vector data in a virtual globe. Trans. GIS 24(4): 1033-1046 (2020) - [c147]Dawen Xu, Ziyang Zhu, Cheng Liu, Ying Wang, Huawei Li, Lei Zhang, Kwang-Ting Cheng:
Persistent Fault Analysis of Neural Networks on FPGA-based Acceleration System. ASAP 2020: 85-92 - [c146]Yintao He, Ying Wang, Xiandong Zhao, Huawei Li, Xiaowei Li:
Towards State-Aware Computation in ReRAM Neural Networks. DAC 2020: 1-6 - [c145]Yongchen Wang, Ying Wang, Huawei Li, Yinhe Han, Xiaowei Li:
An Efficient Deep Learning Accelerator for Compressed Video Analysis. DAC 2020: 1-6 - [c144]Dawen Xu, Kexin Chu, Cheng Liu, Ying Wang, Lei Zhang, Huawei Li:
CNT-Cache: an Energy-Efficient Carbon Nanotube Cache with Adaptive Encoding. DATE 2020: 963-966 - [c143]Jiaqi Zhang, Ying Zhang, Huawei Li, Jianhui Jiang:
HIT: A Hidden Instruction Trojan Model for Processors. DATE 2020: 1271-1274 - [c142]Dawen Xu, Cheng Chu, Cheng Liu, Ying Wang, Xianzhong Zhou, Lei Zhang, Huaguo Liang, Huawei Li:
Multi-task Scheduling for PIM-based Heterogeneous Computing System. ACM Great Lakes Symposium on VLSI 2020: 457-462 - [c141]Qingli Guo, Jing Ye, Jiliang Zhang, Yu Hu, Xiaowei Li, Huawei Li:
Prediction Stability: A New Metric for Quantitatively Evaluating DNN Outputs. ACM Great Lakes Symposium on VLSI 2020: 537-542 - [c140]Shengwen Liang, Cheng Liu, Ying Wang, Huawei Li, Xiaowei Li:
DeepBurning-GL: an Automated Framework for Generating Graph Neural Network Accelerators. ICCAD 2020: 1-9 - [c139]Ying Wang, Mengdi Wang, Bing Li, Huawei Li, Xiaowei Li:
A Many-Core Accelerator Design for On-Chip Deep Reinforcement Learning. ICCAD 2020: 1-7 - [c138]Rajendra Bishnoi, Lizhou Wu, Moritz Fieback, Christopher Münch, Sarath Mohanachandran Nair, Mehdi Baradaran Tahoori, Ying Wang, Huawei Li, Said Hamdioui:
Special Session - Emerging Memristor Based Memory and CIM Architecture: Test, Repair and Yield Analysis. VTS 2020: 1-10 - [c137]Zizhen Liu, Jing Ye, Xing Hu, Huawei Li, Xiaowei Li, Yu Hu:
Sequence Triggered Hardware Trojan in Neural Network Accelerator. VTS 2020: 1-6 - [c136]Qidong Wang, Aijiao Cui, Gang Qu, Huawei Li:
A New Secure Scan Design with PUF-based Key for Authentication. VTS 2020: 1-6
2010 – 2019
- 2019
- [j56]Xiaowei Li, Wenjie Li, Jing Ye, Huawei Li, Yu Hu:
Scan Chain Based Attacks and Countermeasures: A Survey. IEEE Access 7: 85055-85065 (2019) - [j55]Yibin Tang, Ying Wang, Huawei Li, Xiaowei Li:
MV-Net: Toward Real-Time Deep Learning on Mobile GPGPU Systems. ACM J. Emerg. Technol. Comput. Syst. 15(4): 35:1-35:25 (2019) - [j54]Yun Cheng, Huawei Li, Ying Wang, Xiaowei Li:
Cluster Restoration-Based Trace Signal Selection for Post-Silicon Debug. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(4): 767-779 (2019) - [j53]Ying Wang, Huawei Li, Long Cheng, Xiaowei Li:
A QoS-QoR Aware CNN Accelerator Design Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(11): 1995-2007 (2019) - [j52]Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark Mohammad Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber:
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 253-280 (2019) - [c135]Dawen Xu, KouZi Xing, Cheng Liu, Ying Wang, Yulin Dai, Long Cheng, Huawei Li, Lei Zhang:
Resilient Neural Network Training for Accelerators with Computing Errors. ASAP 2019: 99-102 - [c134]Dawen Xu, Li Li, Ying Wang, Cheng Liu, Huawei Li:
Exploring emerging CNFET for efficient last level cache design. ASP-DAC 2019: 426-431 - [c133]Wen Li, Ying Wang, Huawei Li, Xiaowei Li:
P3M: a PIM-based neural network model protection scheme for deep learning accelerator. ASP-DAC 2019: 633-638 - [c132]Renjie Lu, Haihua Shen, Yu Su, Huawei Li, Xiaowei Li:
GramsDet: Hardware Trojan Detection Based on Recurrent Neural Network. ATS 2019: 111-116 - [c131]Ying Wang, Shengwen Liang, Huawei Li, Xiaowei Li:
A None-Sparse Inference Accelerator that Distills and Reuses the Computation Redundancy in CNNs. DAC 2019: 202 - [c130]Yongchen Wang, Ying Wang, Huawei Li, Cong Shi, Xiaowei Li:
Systolic Cube: A Spatial 3D CNN Accelerator Architecture for Low Power Video Analysis. DAC 2019: 210 - [c129]Kaiwei Zou, Ying Wang, Huawei Li, Xiaowei Li:
Learn-to-Scale: Parallelizing Deep Learning Inference on Chip Multiprocessor Architecture. DATE 2019: 1172-1177 - [c128]Shengwen Liang, Ying Wang, Cheng Liu, Huawei Li, Xiaowei Li:
InS-DLA: An In-SSD Deep Learning Accelerator for Near-Data Processing. FPL 2019: 173-179 - [c127]Yintao He, Ying Wang, Yongchen Wang, Huawei Li, Xiaowei Li:
An Agile Precision-Tunable CNN Accelerator based on ReRAM. ICCAD 2019: 1-7 - [c126]Wen Li, Ying Wang, Huawei Li, Xiaowei Li:
RRAMedy: Protecting ReRAM-Based Neural Network from Permanent and Soft Faults During Its Lifetime. ICCD 2019: 91-99 - [c125]Jing Chen, Hui Zheng, Peng Li, Zhenjiang Zhang, Huawei Li, Wei Liu:
Fuzzy Association Rule Mining Algorithm Based on Load Classifier. ICDS 2019: 178-191 - [c124]Huawei Li, Zhihuai Li, Na Tian:
Resource Bottleneck Analysis of the Blockchain Based on Tron's TPS. ICNC-FSKD 2019: 944-950 - [c123]Kuozhong Zhang, Junying Huang, Jing Ye, Xiaochun Ye, Da Wang, Dongrui Fan, Huawei Li, Xiaowei Li, Zhimin Zhang:
iATPG: Instruction-level Automatic Test Program Generation for Vulnerabilities under DVFS attack. IOLTS 2019: 287-292 - [c122]Kuen-Jong Lee, Shi-Yu Huang, Huawei Li, Tomoo Inoue, Yervant Zorian:
International Test Conference in Asia (ITC-Asia) - Bridging ITC and Test Community in Asia. ITC 2019: 1-4 - [c121]Huawei Li, Xiaowei Li, Yinhe Han:
China Test Conference (CTC) - Extending the Global Test Forum to China. ITC 2019: 1-4 - [c120]Yipei Yang, Jing Ye, Xiaowei Li, Yinhe Han, Huawei Li, Yu Hu:
Implementation of Parametric Hardware Trojan in FPGA. ITC-Asia 2019: 37-42 - [c119]Junying Huang, Jing Ye, Xiaochun Ye, Da Wang, Dongrui Fan, Huawei Li, Xiaowei Li, Zhimin Zhang:
Instruction Vulnerability Test and Code Optimization Against DVFS Attack. ITC-Asia 2019: 49-54 - [c118]Li Li, Dawen Xu, Kouzi Xing, Cheng Liu, Ying Wang, Huawei Li, Xiaowei Li:
Squeezing the Last MHz for CNN Acceleration on FPGAs. ITC-Asia 2019: 151-156 - [c117]Aijiao Cui, Zhenxing Chang, Ziming Wang, Gang Qu, Huawei Li:
A Memristor-based Scan Hold Flip-Flop. NVMSA 2019: 1-2 - [c116]Shengwen Liang, Ying Wang, Youyou Lu, Zhe Yang, Huawei Li, Xiaowei Li:
Cognitive SSD: A Deep Learning Engine for In-Storage Data Retrieval. USENIX Annual Technical Conference 2019: 395-410 - [c115]Aijiao Cui, Yan Yang, Gang Qu, Huawei Li:
A Secure and Low-overhead Active IC Metering Scheme. VTS 2019: 1-6 - [c114]Wen Li, Ying Wang, Huawei Li, Xiaowei Li:
Leveraging Memory PUFs and PIM-based encryption to secure edge deep learning systems. VTS 2019: 1-6 - [i1]Renjie Lu, Haihua Shen, Feng Zhang, Huawei Li, Wei Zhao, Xiaowei Li:
HTDet: A Clustering Method using Information Entropy for Hardware Trojan Detection. CoRR abs/1906.06996 (2019) - 2018
- [j51]Faqiang Sun, Guihai Yan, Xin He, Huawei Li, Yinhe Han:
CPicker: Leveraging Performance-Equivalent Configurations to Improve Data Center Energy Efficiency. J. Comput. Sci. Technol. 33(1): 131-144 (2018) - [j50]Ying Wang, Huawei Li, Yinhe Han, Xiaowei Li:
A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multiprocessors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(6): 1265-1277 (2018) - [j49]Ying Wang, Huawei Li, Xiaowei Li:
A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(10): 1971-1984 (2018) - [j48]Yun Cheng, Huawei Li, Ying Wang, Haihua Shen, Bo Liu, Xiaowei Li:
On Trace Buffer Reuse-Based Trigger Generation in Post-Silicon Debug. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(10): 2166-2179 (2018) - [j47]Haihua Shen, Huazhe Tan, Huawei Li, Feng Zhang, Xiaowei Li:
LMDet: A "Naturalness" Statistical Method for Hardware Trojan Detection. IEEE Trans. Very Large Scale Integr. Syst. 26(4): 720-732 (2018) - [c113]Wenjie Li, Jing Ye, Xiaowei Li, Huawei Li, Yu Hu:
Bias PUF based Secure Scan Chain Design. AsianHOST 2018: 31-36 - [c112]Kaiwei Zou, Ying Wang, Huawei Li, Xiaowei Li:
XORiM: A case of in-memory bit-comparator implementation and its performance implications. ASP-DAC 2018: 349-354 - [c111]Wenxuan Wang, Aijiao Cui, Gang Qu, Huawei Li:
A low-overhead PUF based on parallel scan design. ASP-DAC 2018: 715-720 - [c110]Wei Zhao, Haihua Shen, Huawei Li, Xiaowei Li:
Hardware Trojan Detection Based on Signal Correlation. ATS 2018: 80-85 - [c109]Aijiao Cui, Wei Zhou, Gang Qu, Huawei Li:
A New Scheme to Extract PUF Information by Scan Chain. ATS 2018: 104-108 - [c108]Ying Wang, Zhenyu Quan, Jiajun Li, Yinhe Han, Huawei Li, Xiaowei Li:
A retrospective evaluation of energy-efficient object detection solutions on embedded devices. DATE 2018: 709-714 - [c107]Dawen Xu, Kaijie Tu, Ying Wang, Cheng Liu, Bingsheng He, Huawei Li:
FCN-engine: accelerating deconvolutional layers in classic CNN processors. ICCAD 2018: 22 - [c106]Ying Wang, Wen Li, Huawei Li, Xiaowei Li:
Lightweight Timing Channel Protection for Shared DRAM Controller. ITC 2018: 1-10 - [c105]Ying Wang, Wen Li, Huawei Li, Xiaowei Li:
Leveraging DRAM Refresh to Protect the Memory Timing Channel of Cloud Chip Multi-processors. ITC-Asia 2018: 73-78 - [c104]Ying Zhang, Lu Yu, Huawei Li, Jianhui Jiang:
Small Trojan Testing Using Bounded Model Checking. ITC-Asia 2018: 85-90 - [c103]Sohrab Aftabjahani, Jason Oberg, Michael Chen, Huawei Li:
Innovative practices on challenges, opportunities, and solutions to hardware security. VTS 2018: 1 - [c102]Jing Ye, Qingli Guo, Yu Hu, Huawei Li, Xiaowei Li:
Modeling attacks on strong physical unclonable functions strengthened by random number and weak PUF. VTS 2018: 1-6 - 2017
- [j46]Aijiao Cui, Yanhui Luo, Huawei Li, Gang Qu:
Why current secure scan designs fail and how to fix them? Integr. 56: 105-114 (2017) - [j45]Ying Wang, Yinhe Han, Cheng Wang, Huawei Li, Xiaowei Li:
Retention-Aware DRAM Assembly and Repair for Future FGR Memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(5): 705-718 (2017) - [j44]Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark Mohammad Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson:
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 1-20 (2017) - [j43]Lili Song, Ying Wang, Yinhe Han, Huawei Li, Yuanqing Cheng, Xiaowei Li:
STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator. IEEE Trans. Very Large Scale Integr. Syst. 25(4): 1285-1296 (2017) - [j42]Ying Wang, Jiachao Deng, Yuntan Fang, Huawei Li, Xiaowei Li:
Resilience-Aware Frequency Tuning for Neural-Network-Based Approximate Computing Chips. IEEE Trans. Very Large Scale Integr. Syst. 25(10): 2736-2748 (2017) - [c101]Yibin Tang, Ying Wang, Huawei Li, Xiaowei Li:
ApproxPIM: Exploiting realistic 3D-stacked DRAM for energy-efficient processing in-memory. ASP-DAC 2017: 396-401 - [c100]Aijiao Cui, Xuesen Qian, Gang Qu, Huawei Li:
A New Active IC Metering Technique Based on Locking Scan Cells. ATS 2017: 40-45 - [c99]Wei Zhou, Aijiao Cui, Huawei Li, Gang Qu:
How to Secure Scan Design Against Scan-Based Side-Channel Attacks? ATS 2017: 121-126 - [c98]Said Hamdioui, Peyman Pouyan, Huawei Li, Ying Wang, Arijit Raychowdhury, Insik Yoon:
Test and Reliability of Emerging Non-volatile Memories. ATS 2017: 175-183 - [c97]Huina Chao, Huawei Li, Xiaoyu Song, Tiancheng Wang, Xiaowei Li:
On Evaluating and Constraining Assertions Using Conflicts in Absent Scenarios. ATS 2017: 195-200 - [c96]Dawen Xu, Yi Liao, Ying Wang, Huawei Li, Xiaowei Li:
Selective off-loading to Memory: Task Partitioning and Mapping for PIM-enabled Heterogeneous Systems. Conf. Computing Frontiers 2017: 255-258 - [c95]Ying Wang, Huawei Li, Xiaowei Li:
Real-Time Meets Approximate Computing: An Elastic CNN Inference Accelerator with Adaptive Trade-off between QoS and QoR. DAC 2017: 33:1-33:6 - [c94]Zelong Wu, Hui Tang, Sifeng He, Jian Gao, Xin Chen, Chengqiang Cui, Yunbo He, Kai Zhang, Huawei Li, Yangmin Li:
A regularized on-line sequential extreme learning machine with forgetting property for fast dynamic hysteresis modeling. IROS 2017: 383-388 - [c93]Ying Zhang, Krishnendu Chakrabarty, Huawei Li, Jianhui Jiang:
Software-based online self-testing of network-on-chip using bounded model checking. ITC 2017: 1-10 - [c92]Yun Cheng, Huawei Li, Ying Wang, Yingke Gao, Bo Liu, Xiaowei Li:
Flip-flop clustering based trace signal selection for post-silicon debug. VTS 2017: 1-6 - [c91]Huawei Li, Xiaowei Li:
Innovative practices session 10C formal verification practices in industry. VTS 2017: 1 - 2016
- [j41]Jun Zhou, Huawei Li, Tiancheng Wang, Xiaowei Li:
LOFT: A low-overhead fault-tolerant routing scheme for 3D NoCs. Integr. 52: 41-50 (2016) - [j40]Guihai Yan, Faqiang Sun, Huawei Li, Xiaowei Li:
CoreRank: Redeeming "Sick Silicon" by Dynamically Quantifying Core-Level Healthy Condition. IEEE Trans. Computers 65(3): 716-729 (2016) - [j39]Jian Wang, Huawei Li, Tao Lv, Tiancheng Wang, Xiaowei Li, Sandip Kundu:
Abstraction-Guided Simulation Using Markov Analysis for Functional Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(2): 285-297 (2016) - [j38]Yanhong Zhou, Tiancheng Wang, Huawei Li, Tao Lv, Xiaowei Li:
Functional Test Generation for Hard-to-Reach States Using Path Constraint Solving. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(6): 999-1011 (2016) - [j37]Song Jin, Songwei Pei, Yinhe Han, Huawei Li:
A Cost-Effective Energy Optimization Framework of Multicore SoCs Based on Dynamically Reconfigurable Voltage-Frequency Islands. ACM Trans. Design Autom. Electr. Syst. 21(2): 27:1-27:14 (2016) - [j36]Ying Wang, Yinhe Han, Huawei Li, Xiaowei Li:
VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 858-870 (2016) - [j35]Ying Wang, Yinhe Han, Huawei Li, Lei Zhang, Yuanqing Cheng, Xiaowei Li:
PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM. IEEE Trans. Very Large Scale Integr. Syst. 24(5): 1613-1625 (2016) - [c90]Yingxin Qiu, Huawei Li, Tiancheng Wang, Bo Liu, Yingke Gao, Xiaowei Li:
Property Coverage Analysis Based Trustworthiness Verification for Potential Threats from EDA Tools. ATS 2016: 43-48 - [c89]Ying Wang, Yinhe Han, Jun Zhou, Huawei Li, Xiaowei Li:
DISCO: a low overhead in-network data compressor for energy-efficient chip multi-processors. DAC 2016: 37:1-37:6 - [c88]Ying Wang, Jie Xu, Yinhe Han, Huawei Li, Xiaowei Li:
DeepBurning: automatic generation of FPGA-based learning accelerators for the neural network family. DAC 2016: 110:1-110:6 - [c87]Ying Wang, Huawei Li, Xiaowei Li:
Frequency scheduling for resilient chip multi-processors operating at Near Threshold Voltage. DATE 2016: 1164-1167 - [c86]Faqiang Sun, Huawei Li, Yinhe Han, Guihai Yan, Jun Ma:
PowerCap: Leverage Performance-Equivalent Resource Configurations for power capping. IGSC 2016: 1-8 - [c85]Ying Ren, Lijun Zhou, Huawei Li:
Task Scheduling in Cloud Computing Based on Cross Entropy Method. GRMSE (1) 2016: 196-202 - [c84]Jiadong Wang, Aijiao Cui, Mengyang Li, Gang Qu, Huawei Li:
An ultra-low overhead LUT-based PUF for FPGA. AsianHOST 2016: 1-6 - [c83]Ying Wang, Huawei Li, Xiaowei Li:
Re-architecting the on-chip memory sub-system of machine-learning accelerator for embedded devices. ICCAD 2016: 13 - [c82]Yanhui Luo, Aijiao Cui, Gang Qu, Huawei Li:
A new countermeasure against scan-based side-channel attacks. ISCAS 2016: 1722-1725 - [c81]Huina Chao, Huawei Li, Tiancheng Wang, Xiaowei Li, Bo Liu:
An accurate algorithm for computing mutation coverage in model checking. ITC 2016: 1-10 - [c80]Yanhong Zhou, Huawei Li, Tiancheng Wang, Bo Liu, Yingke Gao, Xiaowei Li:
Path constraint solving based test generation for observability-enhanced branch coverage. VTS 2016: 1-6 - 2015
- [j34]Songwei Pei, Huawei Li, Song Jin, Jun Liu, Xiaowei Li:
An on-chip frequency programmable test clock generation and application method for small delay defect detection. Integr. 49: 87-97 (2015) - [j33]Huawei Li, Jing Wu:
Survey of WDM network reconfiguration: topology migrations and their impact on service disruptions. Telecommun. Syst. 60(3): 349-366 (2015) - [j32]Ying Wang, Yinhe Han, Lei Zhang, Binzhang Fu, Cheng Liu, Huawei Li, Xiaowei Li:
Economizing TSV Resources in 3-D Network-on-Chip Design. IEEE Trans. Very Large Scale Integr. Syst. 23(3): 493-506 (2015) - [j31]Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li:
Data Remapping for Static NUCA in Degradable Chip Multiprocessors. IEEE Trans. Very Large Scale Integr. Syst. 23(5): 879-892 (2015) - [c79]Songwei Pei, Ye Geng, Huawei Li, Jun Liu, Song Jin:
Enhanced LCCG: A novel test clock generation scheme for faster-than-at-speed delay testing. ASP-DAC 2015: 514-519 - [c78]Guopei Liu, Ying Wang, Sen Li, Huawei Li, Xiaowei Li:
A Lightweight Timing Channel Protection for Shared Memory Controllers. ATS 2015: 55-60 - [c77]Jun Zhou, Huawei Li, Tiancheng Wang, Sen Li, Ying Wang, Xiaowei Li:
TWiN: A Turn-Guided Reliable Routing Scheme for Wireless 3D NoCs. ATS 2015: 85-90 - [c76]Jun Zhou, Huawei Li, Tiancheng Wang, Ying Wang, Xiaowei Li:
TURO: A lightweight turn-guided routing scheme for 3D NoCs. COOL Chips 2015: 1-3 - [c75]Ying Wang, Yinhe Han, Cheng Wang, Huawei Li, Xiaowei Li:
RADAR: a case for retention-aware DRAM assembly and repair in future FGR DRAM memory. DAC 2015: 19:1-19:6 - [c74]Ying Wang, Yinhe Han, Lei Zhang, Huawei Li, Xiaowei Li:
ProPRAM: exploiting the transparent logic resources in non-volatile memory for near data computing. DAC 2015: 47:1-47:6 - [c73]Ying Zhang, Zebo Peng, Jianhui Jiang, Huawei Li, Masahiro Fujita:
Temperature-aware software-based self-testing for delay faults. DATE 2015: 423-428 - [c72]Jiachao Deng, Yuntan Fang, Zidong Du, Ying Wang, Huawei Li, Olivier Temam, Paolo Ienne, David Novo, Xiaowei Li, Yunji Chen, Chengyong Wu:
Retraining-based timing error mitigation for hardware neural networks. DATE 2015: 593-596 - [c71]Ying Wang, Lili Song, Yinhe Han, Yuanqing Cheng, Huawei Li, Xiaowei Li:
A case of precision-tunable STT-RAM memory design for approximate neural network. ISCAS 2015: 1534-1537 - [c70]Yun Cheng, Ying Wang, Huawei Li, Xiaowei Li:
A Similarity Based Circuit Partitioning and Trimming Method to Defend against Hardware Trojans. ISVLSI 2015: 368-373 - [c69]Song Jin, Songwei Pei, Yinhe Han, Huawei Li:
On optimizing system energy of multi-core SoCs based on dynamically reconfigurable voltage-frequency island. VLSI-DAT 2015: 1-4 - 2014
- [j30]Ying Wang, Lei Zang, Yinhe Han, Huawei Li:
Reinventing Memory System Design for Many-Accelerator Architecture. J. Comput. Sci. Technol. 29(2): 273-280 (2014) - [j29]Shuangde Fang, Zidong Du, Yuntan Fang, Yuanjie Huang, Yang Chen, Lieven Eeckhout, Olivier Temam, Huawei Li, Yunji Chen, Chengyong Wu:
Performance Portability Across Heterogeneous SoCs Using a Generalized Library-Based Approach. ACM Trans. Archit. Code Optim. 11(2): 21:1-21:25 (2014) - [j28]Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li:
ZoneDefense: A Fault-Tolerant Routing for 2-D Meshes Without Virtual Channels. IEEE Trans. Very Large Scale Integr. Syst. 22(1<