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ORCIDNatalino G. Busá
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2000 – 2009
- 2003
[j2]Bart Mesman, Qin Zhao, Natalino G. Busá, Katarzyna Leijten-Nowak:
Reconfigurable Instruction-Set Application-Tuning for DSP. J. Circuits Syst. Comput. 12(3): 333-352 (2003)- 2002
- [j1]André Nieuwland, Jeffrey Kang, Om Prakash Gangwal, Ramanathan Sethuraman, Natalino G. Busá, Kees Goossens, Rafael Peset Llopis, Paul E. R. Lippens:
C-HEAP: A Heterogeneous Multi-Processor Architecture Template and Scalable and Flexible Protocol for the Design of Embedded Signal Processing Systems. Des. Autom. Embed. Syst. 7(3): 233-270 (2002) - [c5]Carles Rodoreda Sala, Natalino G. Busá:
A Run-Time Word-Level Reconfigurable Coarse-Grain Functional Unit for a VLIW Processor. ISSS 2002: 44-49 - [c4]Natalino G. Busá, Ghiath Alkadi, Michael J. Verberne, Rafael Peset Llopis, Sethuraman Ramanatha:
RAPIDO: A Modular, Multi-Board, Heterogeneous Multi-Processor, PCI Bus Based Prototyping Framework for the Validation of SoC VLSI Designs. IEEE International Workshop on Rapid System Prototyping 2002: 159-165 - 2001
- [c3]Marco Bekooij, Loek J. M. Engels, Albert van der Werf, Natalino G. Busá:
Functional units with conditional input/output behavior in VLIW processors. DATE 2001: 822 - [c2]Ram Lakhan Gupta, Anshul Kumar, Aalbert Van Der Werf, Natalino G. Busá:
Synthesizing A Long Latency Unit Within Vliw Processor. VLSI Design 2001: 460- - 2000
- [c1]Natalino G. Busá, Albert van der Werf, Marco Bekooij:
Scheduling Coarse-Grain Operations for VLIW Processors. ISSS 2000: 47-54
Coauthor Index
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