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ORCIDUmer Farooq 0001
Person information
- affiliation: Dhofar University, College of Engineering, Electrical and Computer Engineering Department, Salalah, Oman
- affiliation (PhD 2011): Universite Pierre et Marie Curie, Department of informatics and electronics, Paris, France
Other persons with the same name
- Umer Farooq — disambiguation page
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2020 – today
- 2023
[j19]Umer Farooq
, Imran Baig, Muhammad Khurram Bhatti, Habib Mehrez, Arun Kumar, Manoj Gupta:
Prototyping using multi-FPGA platform: A novel and complete flow. Microprocess. Microsystems 96: 104751 (2023)- 2021
- [j18]Umer Farooq, Habib Mehrez:
Pre-Silicon Verification Using Multi-FPGA Platforms: A Review. J. Electron. Test. 37(1): 7-24 (2021) - 2020
- [j17]Manaf Zghaibeh, Umer Farooq, Najam Ul Hasan, Imran Baig:
SHealth: A Blockchain-Based Health System With Smart Contracts Capabilities. IEEE Access 8: 70030-70043 (2020) - [j16]Umer Farooq, Bander A. Alzahrani:
Exploring and optimizing partitioning of large designs for multi-FPGA based prototyping platforms. Computing 102(11): 2361-2383 (2020) - [c20]Imran Baig, Umer Farooq, Najam Ul Hasan, Manaf Zghaibeh, Umer Mukhtar Rana, Ahthasham Sajid:
A Precoding Based Power Domain UFMC Waveform for 5G Multi-Access Edge Computing. FMEC 2020: 34-37
2010 – 2019
- 2019
- [j15]Umer Farooq, Najam Ul Hasan, Imran Baig, Muhammad Naeem Shehzad:
Efficient adaptive framework for securing the Internet of Things devices. EURASIP J. Wirel. Commun. Netw. 2019: 210 (2019) - [j14]Umer Farooq, M. Hassan Aslam, Muhammad Usman:
On the comparison of memristor-transistor hybrid and transistor-only heterogeneous FPGAs. J. King Saud Univ. Comput. Inf. Sci. 31(4): 514-527 (2019) - [j13]Muhammad Adeel Pasha, Umer Farooq, Bilal Siddiqui:
A framework for high-level simulation and optimization of fine-grained reconfigurable architectures. Simul. 95(8) (2019) - [c19]Umer Farooq, Najam Ul Hasan, Imran Baig:
Securing Internet of Things (IoT) Through an Adaptive Framework. SSD 2019: 387-392 - [c18]Imran Baig, Umer Farooq, Najam Ul Hasan, Manaf Zghaibeh, Ahthasham Sajid, U. Mukhtar Rana:
A Low PAPR DHT Precoding Based UFMC Scheme for 5G Communication Systems. CoDIT 2019: 425-428 - [c17]Imran Baig, Umer Farooq, Najam Ul Hasan, Manaf Zghaibeh, Varun Jeoti, Muhammad Imran:
A Low PAPR Universal Filtered Multi-Carrier System for 5G Machine Type Communications. Wireless Days 2019: 1-4 - 2018
- [j12]Umer Farooq, Imran Baig, Bander A. Alzahrani:
An Efficient Inter-FPGA Routing Exploration Environment for Multi-FPGA Systems. IEEE Access 6: 56301-56310 (2018) - [j11]Muhammad Khurram Bhatti, Isil Öz, Sarah Amin, Maria Mushtaq, Umer Farooq, Konstantin Popov, Mats Brorsson:
Locality-aware task scheduling for homogeneous parallel computing systems. Computing 100(6): 557-595 (2018) - [j10]Umer Farooq, Habib Mehrez, Muhammad Khurram Bhatti:
Inter-FPGA interconnect topologies exploration for multi-FPGA systems. Des. Autom. Embed. Syst. 22(1-2): 117-140 (2018) - [j9]Imran Baig, Umer Farooq, Ejaz Ahmed, Muhammad Imran, Muhammad Shoaib:
A hybrid precoding- and filtering-based uplink MC-LNOMA scheme for 5G cellular networks with reduced PAPR. Trans. Emerg. Telecommun. Technol. 29(10) (2018) - [j8]Umer Farooq, Roselyne Chotin-Avot, Muhammad Moazam Azeem, Maminionja Ravoson, Habib Mehrez:
Novel architectural space exploration environment for multi-FPGA based prototyping systems. Microprocess. Microsystems 56: 169-183 (2018) - [j7]Qaisar Bashir, Muhammad Naeem Shehzad, Muhammad Naeem Awais, Umer Farooq, Mirza Tariq Hamayun, Irfan Ali:
A scheduling based energy-aware core switching technique to avoid thermal threshold values in multi-core processing systems. Microprocess. Microsystems 61: 296-305 (2018) - [c16]Maria Mushtaq, Ayaz Akram, Muhammad Khurram Bhatti, Maham Chaudhry, Muhammad Muneeb Yousaf, Umer Farooq, Vianney Lapotre, Guy Gogniat:
Machine Learning For Security: The Case of Side-Channel Attack Detection at Run-time. ICECS 2018: 485-488 - [c15]Imran Baig, Umer Farooq, Najam Ul Hasan, Manaf Zghaibeh, U. Mukhtar Rana, Muhammad Imran, Muhammad Ayaz:
A Joint Filtering and Precoding Based Uplink MC-NOMA. ISNCC 2018: 1-4 - 2017
- [j6]Umer Farooq, M. Faisal Aslam:
Comparative analysis of different AES implementation techniques for efficient resource usage and better performance of an FPGA. J. King Saud Univ. Comput. Inf. Sci. 29(3): 295-302 (2017) - [c14]Muhammad Adeel Pasha, Umer Farooq, Muhammad Ali, Bilal Siddiqui:
A Framework for High Level Simulation and Optimization of Coarse-Grained Reconfigurable Architectures. ARC 2017: 129-137 - [c13]Umer Farooq, Habib Mehrez, Muhammad Khurram Bhatti:
Comparison of direct and switch-based inter-FPGA routing interconnect for multi-FPGA systems. ReConFig 2017: 1-6 - 2016
- [j5]Malik Mubashir Hassan, Umer Farooq:
Adaptive and ubiquitous video streaming over Wireless Mesh Networks. J. King Saud Univ. Comput. Inf. Sci. 28(4): 432-446 (2016) - [c12]Umer Farooq, Roselyne Chotin-Avot, Muhammad Moazam Azeem, Zouha Cherif, Maminionja Ravoson, Saqib Khan, Habib Mehrez:
Using Timing-Driven Inter-FPGA Routing for Multi-FPGA Prototyping Exploration. DSD 2016: 641-645 - [c11]Umer Farooq, Muhammad Khurram Bhatti, M. Hassan Aslam:
A novel heterogeneous FPGA architecture based on memristor-transistor hybrid approach. DTIS 2016: 1-6 - [c10]Muhammad Moazam Azeem, Roselyne Chotin-Avot, Umer Farooq, Maminionja Ravoson, Habib Mehrez:
Multiple FPGAs based prototyping and debugging with complete design flow. IDT 2016: 171-176 - [c9]Umer Farooq, Roselyne Chotin-Avot, Muhammad Moazam Azeem, Maminionja Ravoson, Mariem Turki, Habib Mehrez:
Inter-FPGA routing environment for performance exploration of multi-FPGA systems. RSP 2016: 107-113 - 2015
- [c8]Muhammad Adeel Pasha, Bilal Siddiqui, Umer Farooq:
A design-flow for high-level synthesis and resource estimation of reconfigurable architectures. DTIS 2015: 1-6 - 2014
- [c7]Vinod Pangracious, Zied Marrakchi, Nizar Beltaief, Habib Mehrez, Umer Farooq:
Exploration and optimization of heterogeneous interconnect fabric of 3D tree-based FPGA. DTIS 2014: 1-6 - 2013
- [j4]Umer Farooq, Husain Parvez, Habib Mehrez, Zied Marrakchi:
Exploration and optimization of a homogeneous tree-based application specific inflexible FPGA. Microelectron. J. 44(12): 1052-1062 (2013) - [c6]Vinod Pangracious, Habib Mehrez, Umer Farooq, Zied Marrakchi:
High performance 3-dimensional heterogeneous tree-based FPGA architectures (HT-FPGA). FPGAworld 2013: 3:1-3:6 - [c5]Vinod Pangracious, Habib Mehrez, Nizar Beltaief, Zied Marrakchi, Umer Farooq:
Exploration environment for 3D heterogeneous tree-based FPGA architectures (3D HT-FPGA). ReConFig 2013: 1-6 - 2012
- [j3]Umer Farooq, Husain Parvez, Habib Mehrez, Zied Marrakchi:
A new heterogeneous tree-based application specific FPGA and its comparison with mesh-based application specific FPGA. Microprocess. Microsystems 36(8): 588-605 (2012) - 2011
- [j2]Umer Farooq, Husain Parvez, Habib Mehrez, Zied Marrakchi:
Exploration of Heterogeneous FPGA Architectures. Int. J. Reconfigurable Comput. 2011: 121404:1-121404:18 (2011) - [c4]Umer Farooq, Husain Parvez, Zied Marrakchi, Habib Mehrez:
Comparison between Heterogeneous Mesh-Based and Tree-Based Application Specific FPGA. ARC 2011: 218-229 - 2010
- [c3]Umer Farooq, Husain Parvez, Zied Marrakchi, Habib Mehrez:
Exploration of Heterogeneous FPGA Architectures. ReCoSoC 2010: 37-44
2000 – 2009
- 2009
- [j1]Zied Marrakchi, Hayder Mrabet, Umer Farooq, Habib Mehrez:
FPGA Interconnect Topologies Exploration. Int. J. Reconfigurable Comput. 2009: 259837:1-259837:13 (2009) - 2008
- [c2]Husain Parvez, Zied Marrakchi, Umer Farooq, Habib Mehrez:
A new coarse-grained FPGA architecture exploration environment. FPT 2008: 285-288 - [c1]Umer Farooq, Zied Marrakchi, Hayder Mrabet, Habib Mehrez:
The Effect of LUT and Cluster Size on a Tree Based FPGA Architecture. ReConFig 2008: 115-120
Coauthor Index
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