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ORCIDJosé-Alejandro López Alcantud
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Journal Articles
- 2020
[j2]Ginés Doménech-Asensi
, Juan Zapata-Pérez, Ramón Ruiz Merino, José-Alejandro López Alcantud, José Ángel Díaz-Madrid, Víctor Manuel Brea Sánchez, Paula López:
All-hardware SIFT implementation for real-time VGA images feature extraction. J. Real Time Image Process. 17(2): 371-382 (2020)- 2018
- [j1]Pablo Rubio-Ibáñez, Ramón Ruiz Merino, Ginés Doménech-Asensi, J. Javier Martínez-Álvarez, Juan Zapata-Pérez, José Ángel Díaz-Madrid, José-Alejandro López Alcantud:
An all-hardware implementation of the subpixel refinement stage in SIFT algorithm. Int. J. Circuit Theory Appl. 46(9): 1690-1702 (2018)
Conference and Workshop Papers
- 2017
- [c6]José Ángel Díaz-Madrid, Ginés Doménech-Asensi, José-Alejandro López Alcantud, M. Oberst:
An 11-bit 20-MSample/s pipelined ADC with OTA bias current regulation to optimize power dissipation. ISCAS 2017: 1-4 - 2012
- [c5]Ginés Doménech-Asensi, F. Martinez-Viviente, J. Illade-Quinteiro, Juan Zapata-Pérez, Ramón Ruiz Merino, José-Alejandro López Alcantud, Juan Martínez-Alajarín, Francisco J. Fernández-Luque, Juan M. Carrillo, Miguel Angel Domínguez:
A fourth order CMOS band pass filter for PIR sensors. ICECS 2012: 268-271 - 2006
- [c4]Ginés Doménech-Asensi, Juan Martínez-Alajarín, Ramón Ruiz Merino, José-Alejandro López Alcantud:
Synthesis on FPAA of a Smart Sthetoscope Analog Subsystem. FPL 2006: 1-5 - 2005
- [c3]Ginés Doménech-Asensi, José-Alejandro López Alcantud, Ramón Ruiz Merino:
Description and Simulation of Bio-inspired Systems Using VHDL-AMS. IWINAC (2) 2005: 357-365 - 2003
- [c2]José-Alejandro López Alcantud, José Ángel Díaz-Madrid, Hans Hauer, Ramón Ruiz Merino:
An Analogue Current-Mode Hardware Design Proposal for Preprocessing Layers in ART-Based Neural Networks. IWANN (2) 2003: 97-104 - 2000
- [c1]José-Alejandro López Alcantud, Tom Kazmierski:
VHDL-AMS modeling of self-organizing neural systems. ISCAS 2000: 734-737
Coauthor Index
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