BibTeX records: Kah-Hyong Chang

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@inproceedings{DBLP:conf/isicir/SaisundarYC16,
  author    = {S. Saisundar and
               N. Yoshio and
               Kah{-}Hyong Chang},
  title     = {A rail-to-rail noise-shaping non-binary {SAR} {ADC}},
  booktitle = {International Symposium on Integrated Circuits, {ISIC} 2016, Singapore,
               December 12-14, 2016},
  pages     = {1--4},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISICIR.2016.7829678},
  doi       = {10.1109/ISICIR.2016.7829678},
  timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
  biburl    = {https://dblp.org/rec/conf/isicir/SaisundarYC16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tcas/LiuZWCLLLLYWZGK15,
  author    = {Xin Liu and
               Jun Zhou and
               Chao Wang and
               Kah{-}Hyong Chang and
               Jianwen Luo and
               Jingjing Lan and
               Lei Liao and
               Yat{-}Hei Lam and
               Yongkui Yang and
               Bo Wang and
               Xin Zhang and
               Wang Ling Goh and
               Tony Tae{-}Hyoung Kim and
               Minkyu Je},
  title     = {An Ultralow-Voltage Sensor Node Processor With Diverse Hardware Acceleration
               and Cognitive Sampling for Intelligent Sensing},
  journal   = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
  volume    = {62-II},
  number    = {12},
  pages     = {1149--1153},
  year      = {2015},
  url       = {https://doi.org/10.1109/TCSII.2015.2468927},
  doi       = {10.1109/TCSII.2015.2468927},
  timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/tcas/LiuZWCLLLLYWZGK15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/ChangR15,
  author    = {Kah{-}Hyong Chang and
               Paramesran Raveendran},
  title     = {A Configurable Architecture for Fast Moments Computation},
  journal   = {J. Signal Process. Syst.},
  volume    = {78},
  number    = {2},
  pages     = {179--186},
  year      = {2015},
  url       = {https://doi.org/10.1007/s11265-013-0857-9},
  doi       = {10.1007/s11265-013-0857-9},
  timestamp = {Thu, 12 Mar 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/journals/vlsisp/ChangR15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tcsv/ChangRAL12,
  author    = {Kah{-}Hyong Chang and
               Paramesran Raveendran and
               Barmak Honarvar Shakibaei Asli and
               Chern{-}Loon Lim},
  title     = {Efficient Hardware Accelerators for the Computation of Tchebichef
               Moments},
  journal   = {{IEEE} Trans. Circuits Syst. Video Technol.},
  volume    = {22},
  number    = {3},
  pages     = {414--425},
  year      = {2012},
  url       = {https://doi.org/10.1109/TCSVT.2011.2163980},
  doi       = {10.1109/TCSVT.2011.2163980},
  timestamp = {Tue, 25 Aug 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/tcsv/ChangRAL12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}