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Victor Navarro-Botello

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Journal Articles

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2014
[j4]
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  - journals/mj/Montiel-NelsonNSB14
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  - https://dblp.org/rec/journals/mj/Montiel-NelsonNSB14
Juan A. Montiel-Nelson, Victor Navarro-Botello, Javier Sosa, Tomás Bautista:
Analysis and optimization of dynamically reconfigurable regenerative comparators for ultra-low power 6-bit TC-ADCs in 90 nm CMOS technologies. Microelectron. J. 45(10): 1247-1253 (2014)
2007
[j3]
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Victor Navarro-Botello, Juan A. Montiel-Nelson, Saeid Nooshabadi:
High performance low power CMOS dynamic logic for arithmetic circuits. Microelectron. J. 38(4-5): 482-488 (2007)
[j2]
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Victor Navarro-Botello, Juan A. Montiel-Nelson, Saeid Nooshabadi:
Analysis of High-Performance Fast Feedthrough Logic Families in CMOS. IEEE Trans. Circuits Syst. II Express Briefs 54-II(6): 489-493 (2007)
2006
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Victor Navarro-Botello, Juan A. Montiel-Nelson, Saeid Nooshabadi:
Low Power and High Performance Arithmetic Circuits in Feedthrough CMOS Logic Family for Low Power Applications. J. Low Power Electron. 2(2): 300-307 (2006)

Conference and Workshop Papers

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2009
[c1]
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Héctor Navarro, Saeid Nooshabadi, Juan A. Montiel-Nelson, Victor Navarro-Botello, Javier Sosa, José C. García:
A geometric approach to register transfer level satisfiability. ISQED 2009: 272-275

Coauthor Index

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