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ORCIDTetsufumi Tanamoto
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2020 – today
- 2020
[j4]Tetsufumi Tanamoto, Chika Tanaka, Shinichi Takagi:
SPICE simulation of 32-kHz crystal-oscillator operation based on Si tunnel FET. IEICE Electron. Express 17(6): 20200025 (2020)
2010 – 2019
- 2018
- [j3]Tetsufumi Tanamoto, Chika Tanaka, Satoshi Takaya, Masato Koyama:
SPICE simulation of tunnel FET aiming at 32 kHz crystal-oscillator operation. IEICE Electron. Express 15(3): 20171232 (2018) - 2017
- [j2]Tetsufumi Tanamoto
, Shinichi Yasuda, Satoshi Takaya, Shinobu Fujita:
Physically Unclonable Function Using an Initial Waveform of Ring Oscillators. IEEE Trans. Circuits Syst. II Express Briefs 64-II(7): 827-831 (2017) - [i5]Tetsufumi Tanamoto, Satoshi Takaya, Nobuaki Sakamoto, Hirotsugu Kasho, Shinichi Yasuda, Takao Marukame, Shinobu Fujita, Yuichiro Mitani:
Physically unclonable function using initial waveform of ring oscillators on 65 nm CMOS technology. CoRR abs/1703.00073 (2017) - [i4]Tetsufumi Tanamoto, Chika Tanaka, Satoshi Takaya, Masato Koyama:
SPICE Simulation of tunnel FET aiming at 32 kHz crystal-oscillator operation. CoRR abs/1710.07375 (2017) - 2016
- [i3]Tetsufumi Tanamoto, Shinichi Yasuda, Satoshi Takaya, Shinobu Fujita:
Physically Unclonable Function using Initial Waveform of Ring Oscillators. CoRR abs/1605.03290 (2016) - [i2]Tetsufumi Tanamoto, Naoharu Shimomura, Sumio Ikegawa, Mari Matsumoto, Shinobu Fujita, Hiroaki Yoda:
High-Speed Magnetoresistive Random-Access Memory Random Number Generator Using Error-Correcting Code. CoRR abs/1606.03147 (2016) - 2014
- [c7]Hiroki Noguchi, Kazutaka Ikegami, Naoharu Shimomura, Tetsufumi Tanamoto, Junichi Ito, Shinobu Fujita:
Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU. VLSIC 2014: 1-2 - 2011
- [i1]Tetsufumi Tanamoto, Hideyuki Sugiyama, Tomoaki Inokuchi, Takao Marukame, Mizue Ishikawa, Kazutaka Ikegami, Yoshiaki Saito:
Scalability of spin FPGA: A Reconfigurable Architecture based on spin MOSFET. CoRR abs/1104.1493 (2011) - 2010
- [c6]Shinichi Yasuda, Tetsufumi Tanamoto, Kazutaka Ikegami, Atsuhiro Kinoshita, Keiko Abe, Hirotaka Nishino, Shinobu Fujita:
High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only). FPGA 2010: 291
2000 – 2009
- 2009
- [c5]Shinobu Fujita, Keiko Abe, Kumiko Nomura, Shinichi Yasuda, Tetsufumi Tanamoto:
Perspectives and Issues in 3D-IC from Designers' Point of View. ISCAS 2009: 73-76 - 2008
- [c4]Mari Matsumoto, Shinichi Yasuda, Ryuji Ohba, Kazutaka Ikegami, Tetsufumi Tanamoto, Shinobu Fujita:
1200μm2 Physical Random-Number Generators Based on SiN MOSFET for Secure Smart-Card Application. ISSCC 2008: 414-415 - 2006
- [c3]Ryuji Ohba, Daisuke Matsushita, Koichi Muraoka, Shinichi Yasuda, Tetsufumi Tanamoto, Ken Uchida, Shinobu Fujita:
Si Nanocrystal MOSFET with Silicon Nitride Tunnel Insulator for High-rate Random Number Generation. ISVLSI 2006: 231-236 - [c2]Benjamin Gojman, Raphael Rubin, Concetta Pilotto, André DeHon, Tetsufumi Tanamoto:
3D Nanowire-Based Programmable Logic. Nano-Net 2006: 1-5 - 2005
- [c1]Shinichi Yasuda, Tetsufumi Tanamoto, Ryuji Ohba, Keiko Abe, Hanae Nozaki, Shinobu Fujita:
Physical random number generators for cryptographic application in mobile devices. ESSCIRC 2005: 399-402 - 2004
- [j1]Shinichi Yasuda, Hideki Satake, Tetsufumi Tanamoto, Ryuji Ohba, Ken Uchida, Shinobu Fujita:
Physical random number generator based on MOS structure after soft breakdown. IEEE J. Solid State Circuits 39(8): 1375-1377 (2004)
Coauthor Index
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