BibTeX records: Shuilong Huang

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@article{DBLP:journals/ieiceee/WeiXH17,
  author    = {Zihui Wei and
               Yanbin Xiao and
               Shuilong Huang},
  title     = {11b 60 MHz pipelined {ADC} with inverter-based class {AB} amplifier
               in 28 nm {CMOS} technology},
  journal   = {{IEICE} Electron. Express},
  volume    = {14},
  number    = {5},
  pages     = {20170047},
  year      = {2017}
}
@article{DBLP:journals/jcsc/HuangW08,
  author    = {Shuilong Huang and
               Zhihua Wang},
  title     = {System Design Considerations of Highly-Integrated SigmaDelta fractional-n
               Frequency synthesizer},
  journal   = {J. Circuits Syst. Comput.},
  volume    = {17},
  number    = {2},
  pages     = {169--181},
  year      = {2008}
}
@inproceedings{DBLP:conf/date/HuangMW07,
  author    = {Shuilong Huang and
               Huainan Ma and
               Zhihua Wang},
  title     = {Modeling and simulation to the design of SigmaDelta fractional-N frequency
               synthesizer},
  booktitle = {{DATE}},
  pages     = {291--296},
  publisher = {{EDA} Consortium, San Jose, CA, {USA}},
  year      = {2007}
}
@inproceedings{DBLP:conf/iscas/HuangW07,
  author    = {Shuilong Huang and
               Zhihua Wang},
  title     = {A dual-slope {PFD/CP} frequency synthesizer architecture with an adaptive
               self-tuning algorithm},
  booktitle = {{ISCAS}},
  pages     = {3924--3927},
  publisher = {{IEEE}},
  year      = {2007}
}
@inproceedings{DBLP:conf/apccas/HuangWM06,
  author    = {Shuilong Huang and
               Zhihua Wang and
               Huainan Ma},
  title     = {A Fast 1.9 GHz Fractional-N/Integer Frequency Synthesizer with a Self-tuning
               Algorithm},
  booktitle = {{APCCAS}},
  pages     = {203--206},
  publisher = {{IEEE}},
  year      = {2006}
}
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