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2000 – 2009
- 2005
[j1]Woo-Seung Yang, Chong-Min Kyung:
Conscep: a Configurable Soc Emulation Platform for C-based Fast Prototyping. J. Circuits Syst. Comput. 14(1): 137-158 (2005)- [c7]Jae-Gon Lee
, Woo-Seung Yang, Young-Su Kwon, Young-Il Kim, Chong-Min Kyung:
Simulation acceleration of transaction-level models for SoC with RTL sub-blocks. ASP-DAC 2005: 499-502 - 2004
- [c6]Young-Il Kim, Woo-Seung Yang, Young-Su Kwon, Chong-Min Kyung:
Communication-efficient hardware acceleration for fast functional simulation. DAC 2004: 293-298 - 2003
- [c5]Young-Su Kwon, Woo-Seung Yang, Chong-Min Kyung:
Signal Scheduling Driven Circuit Partitioning for Multiple FPGAs with Time-multiplexed Interconnection. VLSI-SOC 2003: 123-128 - 2001
- [c4]Woo-Seung Yang, In-Cheol Park, Chong-Min Kyung:
Low-power high-level synthesis using latches. ASP-DAC 2001: 462-466 - 2000
- [c3]Hansoo Kim, Woo-Seung Yang, Myoung-Cheol Shin, Seung-Jai Min, Seong-Ok Bae, In-Cheol Park:
Multi-thread VLIW processor architecture for HDTV decoding. CICC 2000: 559-562
1990 – 1999
- 1997
- [c2]Joon-Seo Yim, Chang-Jae Park, Woo-Seung Yang, Hun-Seung Oh, Hee-Choul Lee, Hoon Choi, Tae-Hoon Kim, Seungjong Lee, Nara Won, Yung-Hei Lee, In-Cheol Park, Chong-Min Kyung:
Verification methodology of compatible microprocessors. ASP-DAC 1997: 173-180 - [c1]Joon-Seo Yim, Yoon-Ho Hwang, Chang-Jae Park, Hoon Choi, Woo-Seung Yang, Hun-Seung Oh, In-Cheol Park, Chong-Min Kyung:
A C-Based RTL Design Verification Methodology for Complex Microprocessor. DAC 1997: 83-88
Coauthor Index
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