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Sai Charan Vemula

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2023
[j2]
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N. Renugadevi, Stheya Julakanti, Sai Charan Vemula, Somya Bhatnagar, Shirisha Thangallapally:
Low area and high throughput implementation of advanced encryption standard hardware accelerator on FPGA using Mux-Demux pair. Secur. Priv. 6(4) (2023)
2022
[j1]
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N. Renugadevi, Shirisha Thangallapally, Sai Charan Vemula, Stheya Julakanti, Somya Bhatnagar:
Methods for improving the implementation of advanced encryption standard hardware accelerator on field programmable gate array-A survey. Secur. Priv. 5(6) (2022)

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