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2010 – 2019
- 2019
[c15]Dunmin Zheng, Santanu Dutta:
Adaptive Beamforming for Mobile Satellite Systems Based on User Location/Waveform. VTC Fall 2019: 1-6- 2018
- [j15]Santanu Dutta, Suparna Biswas:
Nonparametric estimation of 100(1 - p)% expected shortfall: p → 0 as sample size is increased. Commun. Stat. Simul. Comput. 47(2): 338-352 (2018) - 2017
- [j14]Santanu Dutta, Suparna Biswas:
Extreme quantile estimation based on financial time series. Commun. Stat. Simul. Comput. 46(6): 4226-4243 (2017) - 2016
- [j13]Santanu Dutta:
Cross-validation Revisited. Commun. Stat. Simul. Comput. 45(2): 472-490 (2016) - 2015
- [j12]Santanu Dutta:
Local Smoothing for Kernel Distribution Function Estimation. Commun. Stat. Simul. Comput. 44(4): 878-891 (2015) - 2014
- [j11]Santanu Dutta:
Local Smoothing Using the Bootstrap. Commun. Stat. Simul. Comput. 43(2): 378-389 (2014) - 2013
- [j10]Subir Ghosh, Santanu Dutta
:
Robustness of designs for model discrimination. J. Multivar. Anal. 115: 193-203 (2013)
2000 – 2009
- 2009
- [j9]Arif Ansari, Santanu Dutta, Michael Tseytlin:
S-WiMAX: adaptation of IEEE 802.16e for mobile satellite services. IEEE Commun. Mag. 47(6): 150-155 (2009) - 2007
- [c14]Balaji Raman, Samarjit Chakraborty, Wei Tsang Ooi, Santanu Dutta:
Reducing Data-Memory Footprint of Multimedia Applications by Delay Redistribution. DAC 2007: 738-743 - [c13]Santanu Dutta:
Recent Trends in the Design of Video Signal Processing IPS and Multimedia SoCs. SECRYPT 2007: 13 - 2005
- [c12]Santanu Dutta:
Design of Multimillion-Gate Multimedia SoCs: Where do we stand? ESTIMedia 2005: 4 - 2003
- [c11]Santanu Dutta:
Architecture and Implementation of Multi-Processor SoCs for Advanced Set-Top Box and Digital TV Systems. SBCCI 2003: 145 - 2001
- [j8]Santanu Dutta, Rune Jensen, Alf Rieckmann:
Viper: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV Systems. IEEE Des. Test Comput. 18(5): 21-31 (2001) - [j7]Santanu Dutta:
Architecture and design of NX-2700: a programmable single-chip HDTV all-format-decode-and-display processor. IEEE Trans. Very Large Scale Integr. Syst. 9(2): 313-328 (2001) - [c10]Santanu Dutta:
Design verification of an 18-million-transistor digital television and media processor chip. ICECS 2001: 1495-1499 - 2000
- [c9]Santanu Dutta:
Architecture, Design, and Verification of an 18 Million Transistor Digital Television and Media Processor Chip. PATMOS 2000: 225-232 - [c8]Santanu Dutta, Deepak Singh, Essam Abu-Ghoush, Vijay Mehra:
Architecture and Implementation of a High-Definition Video Co-Processor for Digital Television Applications. VLSI Design 2000: 350-359
1990 – 1999
- 1999
- [j6]Santanu Dutta, Vijay Mehra, Weiwen Zhu, Deepak Singh, Marcel Janssens, Ramakrishna Vengalasetti, Boaz Ben-Nun, Pardha Pothana, Venkat Adusumilli, Nahid King, John Yen-Han Huang, Lie Ling, Chris Nelson, Jai Bannur, Sarah Wu:
Architecture and design of a Talisman-compatible multimedia processor. IEEE Trans. Circuits Syst. Video Technol. 9(4): 565-579 (1999) - [j5]Santanu Dutta, Wayne H. Wolf:
A circuit-driven design methodology for video signal-processing datapath elements. IEEE Trans. Very Large Scale Integr. Syst. 7(2): 229-240 (1999) - 1998
- [j4]Santanu Dutta, Wayne H. Wolf, Andrew Wolfe:
A methodology to evaluate memory architecture design tradeoffs for video signal processors. IEEE Trans. Circuits Syst. Video Technol. 8(1): 36-53 (1998) - [j3]Santanu Dutta, Kevin J. O'Connor, Wayne H. Wolf, Andrew Wolfe:
A design study of a 0.25-μm video signal processor. IEEE Trans. Circuits Syst. Video Technol. 8(4): 501-519 (1998) - 1997
- [c7]Andrew Wolfe, Jason Fritts, Santanu Dutta, Edil S. T. Fernandes:
Datapath Design for a VLIW Video Signal Processor. HPCA 1997: 24-35 - 1996
- [j2]Santanu Dutta, Wayne H. Wolf:
A flexible parallel architecture adapted to block-matching motion-estimation algorithms. IEEE Trans. Circuits Syst. Video Technol. 6(1): 74-86 (1996) - 1995
- [j1]Santanu Dutta, Wayne H. Wolf:
Asymptotic limits of video signal processing architectures. IEEE Trans. Circuits Syst. Video Technol. 5(6): 545-561 (1995) - [c6]Santanu Dutta, Wayne H. Wolf, Andrew Wolfe:
VLSI issues in memory-system design for video signal processors. ICCD 1995: 498-503 - 1994
- [c5]Santanu Dutta, Wayne H. Wolf:
Asymptotic Limits of Video Signal Processing Architectures. ICCD 1994: 622-625 - [c4]Santanu Dutta, Sudip Nag, Kaushik Roy:
ASAP: A Transistor Sizing Tool for Speed Area and Power Optimization of Static CMOS Circuits. ISCAS 1994: 61-64 - 1993
- [c3]Kaushik Roy, Sudip Nag, Santanu Dutta:
Channel Architecture Optimization for Performance and Routability of Row-Based FPGAs. ICCD 1993: 220-223 - 1990
- [c2]Douglas R. Holberg, Santanu Dutta, Lawrence T. Pillage:
DC Parameterized Piecewise-Function Transistor Models for Bipolar and MOS Logic Stage Delay Evaluation. ICCAD 1990: 546-549
1980 – 1989
- 1989
- [c1]Hau-Yung Chen, Santanu Dutta:
A timing model for static CMOS gates. ICCAD 1989: 72-75
Coauthor Index
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last updated on 2022-08-25 05:37 CEST by the dblp team
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