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2020 – today
- 2023
[j51]Yanhong Wang
, Zihao Zhao, Xu Jin, Haotian Zheng, Maohua Nie, Qiaosha Zou, C.-J. Richard Shi:
AutoMap: Automatic Mapping of Neural Networks to Deep Learning Accelerators for Edge Devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(9): 2994-3006 (2023)- [j50]Yanhong Wang, Tianchan Guan, Dimin Niu, Qiaosha Zou, Hongzhong Zheng, C.-J. Richard Shi, Yuan Xie:
Accelerating Distributed GNN Training by Codes. IEEE Trans. Parallel Distributed Syst. 34(9): 2598-2614 (2023) - 2022
- [j49]Rongjin Xu, Dawei Ye, C.-J. Richard Shi:
A 2.0-2.9 GHz ring-based injection-locked clock multiplier using a self-alignment frequency-tracking loop for reference spur reduction. Integr. 84: 1-11 (2022) - [j48]Dawei Ye, Rongjin Xu, C.-J. Richard Shi:
Erratum to "A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain". IEEE J. Solid State Circuits 57(2): 671 (2022) - [j47]Rongjin Xu, Dawei Ye, C.-J. Richard Shi:
Analysis and Design of Digital Injection-Locked Clock Multipliers Using Bang-Bang Phase Detectors. IEEE Trans. Circuits Syst. I Regul. Pap. 69(7): 2832-2844 (2022) - [j46]Yanhong Wang, Qiaosha Zou, Yanmin Tang, Qing Wang, Jing Ding, Xin Wang, C.-J. Richard Shi:
SAIL: A Deep-Learning-Based System for Automatic Gait Assessment From TUG Videos. IEEE Trans. Hum. Mach. Syst. 52(1): 110-122 (2022) - [c94]Renze Gan, Liangjian Lyu, Geng Mu, C.-J. Richard Shi:
A Neural Recording Analog Front-End with Exponentially Tunable Pseudo Resistors and On-Chip Digital Frequency Calibration Loop Achieving 3.4% Deviation of High-Pass Cutoff Frequency in 5-to-500 Hz Range. CICC 2022: 1-2 - [c93]Rongjin Xu, Dawei Ye, Sirou Li, C.-J. Richard Shi:
A 0.021mm2 65nm CMOS 2.5GHz Digital Injection-Locked Clock Multiplier with Injection Pulse Shaping Achieving -79dBc Reference Spur and 0.496mW/GHz Power Efficiency. ISSCC 2022: 214-216 - [i1]Zihao Zhao, Yanhong Wang, Qiaosha Zou, Tie Xu, Fangbo Tao, Jiansong Zhang, Xiaoan Wang, C.-J. Richard Shi, Junwen Luo, Yuan Xie:
The Spike Gating Flow: A Hierarchical Structure Based Spiking Neural Network for Online Gesture Recognition. CoRR abs/2206.01910 (2022) - 2021
- [j45]Dawei Ye, Rongjin Xu, C.-J. Richard Shi:
A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain. IEEE J. Solid State Circuits 56(11): 3360-3374 (2021) - [j44]Junying Hu, C.-J. Richard Shi, Jiang-She Zhang:
Saliency-based YOLO for single target detection. Knowl. Inf. Syst. 63(3): 717-732 (2021) - [j43]Chang Liu, C.-J. Richard Shi:
Design of the Class-E Power Amplifier Considering the Temperature Effect of the Transistor On-Resistance for Sensor Applications. IEEE Trans. Circuits Syst. II Express Briefs 68(5): 1705-1709 (2021) - [c92]Dawei Ye, Yuting Tu, Wenjun Gong, Rongjin Xu, C.-J. Richard Shi:
A Two-Tone Wake-Up Receiver with an Envelope-Detector-First Architecture Using Envelope Biasing and Active Inductor Load Achieving 41/33dB In-Band Rejection to CW/AM Interference. A-SSCC 2021: 1-3 - [c91]Geng Mu, Dawei Ye, Liangjian Lyu, Xiaobin Zhao, C.-J. Richard Shi:
An 8-Channel Analog Front-End with a PVT-lnsensitive Switched-Capacitor and Analog Combo DC Servo Loop Achieving 300mV Tolerance and 0.64s Recovery Time to Electrode-DC Offset for Physiological Signal Recording. CICC 2021: 1-2 - [c90]Shiwei Liu, Zihao Zhao, Yanhong Wang, Qiaosha Zou, Yiyun Zhang, C.-J. Richard Shi:
Systolic-Array Deep-Learning Acceleration Exploring Pattern-Indexed Coordinate-Assisted Sparsity for Real-Time On-Device Speech Processing. ACM Great Lakes Symposium on VLSI 2021: 353-358 - [c89]Xingfa Qiu, Qiaosha Zou, C.-J. Richard Shi:
Single-Pass On-Line Event Detection in Twitter Streams. ICMLC 2021: 522-529 - [c88]Chang Liu, Chun Zhao, C.-J. Richard Shi:
A Fully-Synthesizable Fast-Response Digital LDO Using Automatic Offset Control and Reuse. ISCAS 2021: 1-5 - 2020
- [j42]Haozhe Zhu, Yu Wang, C.-J. Richard Shi:
Tanji: a General-purpose Neural Network Accelerator with Unified Crossbar Architecture. IEEE Des. Test 37(1): 56-63 (2020) - [j41]Haozhe Zhu, Chixiao Chen, Shiwei Liu, Qiaosha Zou, Mingyu Wang, Lihua Zhang, Xiaoyang Zeng, C.-J. Richard Shi:
A Communication-Aware DNN Accelerator on ImageNet Using In-Memory Entry-Counting Based Algorithm-Circuit-Architecture Co-Design in 65-nm CMOS. IEEE J. Emerg. Sel. Topics Circuits Syst. 10(3): 283-294 (2020) - [j40]Liangjian Lyu, Yu Wang, Chixiao Chen, C.-J. Richard Shi:
A 0.6V 1.07 μW/Channel neural interface IC using level-shifted feedback. Integr. 70: 51-59 (2020) - [j39]Dawei Ye, Yu Wang, Yingfei Xiang, Liangjian Lyu, Hao Min, C.-J. Richard Shi:
A Wireless Power and Data Transfer Receiver Achieving 75.4% Effective Power Conversion Efficiency and Supporting 0.1% Modulation Depth for ASK Demodulation. IEEE J. Solid State Circuits 55(5): 1386-1400 (2020) - [j38]Liangjian Lyu, Dawei Ye, C.-J. Richard Shi:
A 340 nW/Channel 110 dB PSRR Neural Recording Analog Front-End Using Replica-Biasing LNA, Level-Shifter Assisted PGA, and Averaged LFP Servo Loop in 65 nm CMOS. IEEE Trans. Biomed. Circuits Syst. 14(4): 811-824 (2020) - [j37]Liangjian Lyu, Dawei Ye, Rongjin Xu, Geng Mu, Heng Zhao, Yingfei Xiang, Yuting Tu, Yiyun Zhang, C.-J. Richard Shi:
A Fully-Integrated 64-Channel Wireless Neural Interfacing SoC Achieving 110 dB AFE PSRR and Supporting 54 Mb/s Symbol Rate, Meter-Range Wireless Data Transmission. IEEE Trans. Circuits Syst. II Express Briefs 67-II(5): 831-835 (2020) - [j36]Aili Wang, C.-J. Richard Shi:
Analysis of Passive Charge Sharing-Based Segmented SAR ADCs. IEEE Trans. Very Large Scale Integr. Syst. 28(5): 1195-1206 (2020) - [c87]Shiwei Liu, Haozhe Zhu, Chixiao Chen, Lihua Zhang, C.-J. Richard Shi:
XNORAM: An Efficient Computing-in-Memory Architecture for Binary Convolutional Neural Networks with Flexible Dataflow Mapping. AICAS 2020: 21-25 - [c86]Yitu Wang, Fan Chen, Linghao Song, C.-J. Richard Shi, Hai Helen Li, Yiran Chen:
ReBoc: Accelerating Block-Circulant Neural Networks in ReRAM. DATE 2020: 1472-1477 - [c85]Yuting Tu, Rongjin Xu, Dawei Ye, Liangjian Lyu, C.-J. Richard Shi:
A 400 MHz, 8-Bit, 1.75-ps Resolution Pipelined-Two-Step Time-to-Digital Converter with Dynamic Time Amplification. ISCAS 2020: 1-4
2010 – 2019
- 2019
- [j35]Chixiao Chen, Xindi Liu, Huwan Peng, Hongwei Ding, C.-J. Richard Shi:
iFPNA: A Flexible and Efficient Deep Learning Processor in 28-nm CMOS Using a Domain-Specific Instruction Set and Reconfigurable Fabric. IEEE J. Emerg. Sel. Topics Circuits Syst. 9(2): 346-357 (2019) - [j34]C.-J. Richard Shi, Aili Wang:
Analysis of Bitwise and Samplewise Switched Passive Charge Sharing SAR ADCs. IEEE Trans. Very Large Scale Integr. Syst. 27(9): 1977-1989 (2019) - [c84]Liangjian Lyu, Yu Wang, Chixiao Chen, C.-J. Richard Shi:
A low-voltage low-power multi-channel neural interface IC using level-shifted feedback technology. ASP-DAC 2019: 13-14 - [c83]Aili Wang, Chixiao Chen, C.-J. Richard Shi:
A 9-bit Resistor-Based All-Digital Temperature Sensor with a SAR-Quantization Embedded Differential Low-Pass Filter in 65nm CMOS Consuming 57pJ with a 2.5 μs Conversion Time. CICC 2019: 1-4 - [c82]Chong Li, Kunyang Jia, Dan Shen, C.-J. Richard Shi, Hongxia Yang:
Hierarchical Representation Learning for Bipartite Graphs. IJCAI 2019: 2873-2879 - [c81]Liangjian Lyu, Dawei Ye, C.-J. Richard Shi:
A 340nW/Channel Neural Recording Analog Front-End using Replica-Biasing LNAs to Tolerate 200mVpp Interfere from 350mV Power Supply. ISCAS 2019: 1-4 - [c80]Dawei Ye, Rongjin Xu, Liangjian Lyu, C.-J. Richard Shi:
A 2.46GHz, -88dBm Sensitivity CMOS Passive Mixer-First Nonlinear Receiver with >50dB Tolerance to In-Band Interferer. ISCAS 2019: 1-4 - [c79]Dawei Ye, Rongjin Xu, C.-J. Richard Shi:
A 2.4GHz 65nm CMOS Mixer-First Receiver Using 4-Stage Cascaded Inverter-Based Envelope-Biased LNAs Achieving 66dB In-Band Interference Tolerance and -83dBm Sensitivity. ISSCC 2019: 414-416 - 2018
- [j33]Chixiao Chen, Hongwei Ding, Huwan Peng, Haozhe Zhu, Yu Wang, C.-J. Richard Shi:
OCEAN: An On-Chip Incremental-Learning Enhanced Artificial Neural Network Processor With Multiple Gated-Recurrent-Unit Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(3): 519-530 (2018) - [j32]Aili Wang, C.-J. Richard Shi:
A 10-bit 50-MS/s SAR ADC with 1 fJ/Conversion in 14 nm SOI FinFET CMOS. Integr. 62: 246-257 (2018) - [c78]Chixiao Chen, Huwan Peng, Xindi Liu, Hongwei Ding, C.-J. Richard Shi:
Exploring the programmability for deep learning processors: from architecture to tensorization. DAC 2018: 15:1-15:6 - [c77]Chong Li, C.-J. Richard Shi:
Constrained Optimization Based Low-Rank Approximation of Deep Neural Networks. ECCV (10) 2018: 746-761 - [c76]Chixiao Chen, Xindi Liu, Huwan Peng, Hongwei Ding, C.-J. Richard Shi:
iFPNA: A Flexible and Efficient Deep Neural Network Accelerator with a Programmable Data Flow Engine in 28nm CMOS. ESSCIRC 2018: 170-173 - [c75]Ailing Piao, Aili Wang, C.-J. Richard Shi:
Pin-Efficient 12-Bit 8-Wire 8-Level Permutation Coding for High-Speed Parallel Wireline Tranceivers. ISCAS 2018: 1-4 - [c74]Yingfei Xiang, Yu Wang, C.-J. Richard Shi:
A 13.56 MHz Active Rectifier With Self-Switching Comparator for Wireless Power Transfer Systems. ISOCC 2018: 54-55 - [c73]Yu Wang, Dawei Ye, Liangjian Lyu, Yingfei Xiang, Hao Min, C.-J. Richard Shi:
A 13.56MHz Wireless Power and Data Transfer Receiver Achieving 75.4% Effective-Power-Conversion Efficiency with 0.1% ASK Modulation Depth and 9.2mW Output Power. ISSCC 2018: 142-144 - 2017
- [j31]Yu Wang, Na Yan, Hao Min, C.-J. Richard Shi:
A High-Efficiency Split-Merge Charge Pump for Solar Energy Harvesting. IEEE Trans. Circuits Syst. II Express Briefs 64-II(5): 545-549 (2017) - [c72]Chixiao Chen, Hongwei Ding, Huwan Peng, Haozhe Zhu, Rui Ma, Peiyong Zhang, Xiaolang Yan, Yu Wang, Mingyu Wang, Hao Min, C.-J. Richard Shi:
OCEAN: An on-chip incremental-learning enhanced processor with gated recurrent neural network accelerators. ESSCIRC 2017: 259-262 - 2016
- [c71]Allen Waters, Aili Wang, C.-J. Richard Shi:
Highly time-interleaved noise-shaped SAR ADC with reconfigurable order. ISCAS 2016: 1026-1029 - [c70]Aili Wang, Allen Waters, C.-J. Richard Shi:
A sub-nW mV-range programmable threshold comparator for near-zero-energy sensing. ISCAS 2016: 1054-1057 - 2015
- [c69]Chong Li, Suriyaprakash Natarajan, C.-J. Richard Shi:
Identifying DC bias conditions for maximum DC current in digitally-assisted analog design. ICECS 2015: 478-481 - 2010
- [j30]Lihong Zhang, Yuping Zhang, Yingtao Jiang, C.-J. Richard Shi:
Symmetry-aware placement algorithm using transitive closure graph representation for analog integrated circuits. Int. J. Circuit Theory Appl. 38(3): 221-241 (2010) - [c68]C.-J. Richard Shi:
Mixed-signal system-on-chip verification using a recursively-verifying-modeling (RVM) methodology. ISCAS 2010: 1432-1435
2000 – 2009
- 2008
- [j29]Lihong Zhang, Nuttorn Jangkrajarng, Sambuddha Bhattacharya, C.-J. Richard Shi:
Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(5): 791-802 (2008) - [j28]Bo Hu, C.-J. Richard Shi:
Simulation of Closely Related Dynamic Nonlinear Systems With Application to Process-Voltage-Temperature Corner Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(5): 883-892 (2008) - [j27]Lingzhi Liu, C.-J. Richard Shi:
Sliced Message Passing: High Throughput Overlapped Decoding of High-Rate Low-Density Parity-Check Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(11): 3697-3710 (2008) - [c67]Lihong Zhang, C.-J. Richard Shi, Yingtao Jiang:
Symmetry-aware placement with transitive closure graphs for analog layout design. ASP-DAC 2008: 180-185 - [c66]Yiyu Shi, Lei He, C.-J. Richard Shi:
Scalable Symbolic Model Order Reduction. BMAS 2008: 112-117 - [c65]Cherry Wakayama, Wolf Kohn, Zelda B. Zabinsky, C.-J. Richard Shi:
A quantum-dot light-harvesting architecture using deterministic phase control. ISCAS 2008: 332-335 - [c64]Yu-Te Liao, C.-J. Richard Shi:
A 6-11GHz multi-phase VCO design with active inductors. ISCAS 2008: 988-991 - 2007
- [j26]Pavel V. Nikitin, C.-J. Richard Shi:
VHDL-AMS based modeling and simulation of mixed-technology microsystems: a tutorial. Integr. 40(3): 261-273 (2007) - [j25]Lili Zhou, Cherry Wakayama, C.-J. Richard Shi:
CASCADE: A Standard Supercell Design Methodology With Congestion-Driven Placement for Three-Dimensional Interconnect-Heavy Very Large-Scale Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7): 1270-1282 (2007) - [c63]Guoyong Shi, Weiwei Chen, C.-J. Richard Shi:
A Graph Reduction Approach to Symbolic Circuit Analysis. ASP-DAC 2007: 197-202 - [c62]Lili Zhou, Cherry Wakayama, Robin Panda, Nuttorn Jangkrajarng, Bo Hu, C.-J. Richard Shi:
Implementing a 2-Gbs 1024-bit 1/2-rate low-density parity-check code decoder in three-dimensional integrated circuits. ICCD 2007: 194-201 - [c61]Ming Su, Lili Zhou, C.-J. Richard Shi:
Maximizing the throughput-area efficiency of fully-parallel low-density parity-check decoding with C-slow retiming and asynchronous deep pipelining. ICCD 2007: 636-643 - 2006
- [j24]Lei Yang, C.-J. Richard Shi:
FROSTY: A program for fast extraction of high-level structural representation from circuit description for industrial CMOS circuits. Integr. 39(4): 311-339 (2006) - [j23]Sambuddha Bhattacharya, Nuttorn Jangkrajarng, C.-J. Richard Shi:
Multilevel symmetry-constraint generation for retargeting large analog layouts. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 945-960 (2006) - [j22]Zhao Li, C.-J. Richard Shi:
SILCA: SPICE-accurate iterative linear-centric analysis for efficient time-domain Simulation of VLSI circuits with strong parasitic couplings. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 1087-1103 (2006) - [j21]Guoyong Shi, Bo Hu, C.-J. Richard Shi:
On symbolic model order reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(7): 1257-1272 (2006) - [j20]C.-J. Richard Shi, Michael W. Tian, Guoyong Shi:
Efficient DC fault simulation of nonlinear analog circuits: one-step relaxation and adaptive simulation continuation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(7): 1392-1400 (2006) - [j19]Zhao Li, C.-J. Richard Shi:
A Quasi-Newton Preconditioned Newton-Krylov Method for Robust and Efficient Time-Domain Simulation of Integrated Circuits With Strong Parasitic Couplings. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2868-2881 (2006) - [j18]Lei Yang, Hui Liu, C.-J. Richard Shi:
Code construction and FPGA implementation of a low-error-floor multi-rate low-density Parity-check code decoder. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(4): 892-904 (2006) - [c60]Lili Zhou, Cherry Wakayama, Nuttorn Jangkrajarng, Bo Hu, C.-J. Richard Shi:
A high-throughput low-power fully parallel 1024-bit 1/2-rate low density parity check code decoder in 3-dimensional integrated circuits. ASP-DAC 2006: 92-93 - [c59]Zhao Li, C.-J. Richard Shi:
A quasi-newton preconditioned Newton-Krylov method for robust and efficient time-domain simulation of integrated circuits with strong parasitic couplings. ASP-DAC 2006: 402-407 - [c58]Nuttorn Jangkrajarng, Lihong Zhang, Sambuddha Bhattacharya, Nathan Kohagen, C.-J. Richard Shi:
Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts. ICCAD 2006: 342-348 - [c57]Bo Hu, C.-J. Richard Shi:
Improved automatic differentiation method for efficient model compiler. ISCAS 2006 - 2005
- [j17]Guoyong Shi, C.-J. Richard Shi:
Model-order reduction by dominant subspace projection: error bound, subspace computation, and circuit applications. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(5): 975-993 (2005) - [c56]Lei Yang, Manyuan Shen, Hui Liu, C.-J. Richard Shi:
An FPGA implementation of low-density parity-check code decoder with multi-rate capability. ASP-DAC 2005: 760-763 - [c55]Sambuddha Bhattacharya, Nuttorn Jangkrajarng, C.-J. Richard Shi:
Template-driven parasitic-aware optimization of analog integrated circuit layouts. DAC 2005: 644-647 - [c54]Zhao Li, C.-J. Richard Shi:
An Efficiently Preconditioned GMRES Method for Fast Parasitic-Sensitive Deep-Submicron VLSI Circuit Simulation. DATE 2005: 752-757 - [c53]Lei Yang, Hui Liu, C.-J. Richard Shi:
VLSI implementation of a low-error-floor and capacity-approaching low-density parity-check code decoder with multi-rate capacity. GLOBECOM 2005: 6 - [c52]Lei Yang, Cherry Wakayama, C.-J. Richard Shi:
Noise aware behavioral modeling of the E-Delta fractional-N frequency synthesizer. ACM Great Lakes Symposium on VLSI 2005: 138-142 - [c51]Bo Hu, C.-J. Richard Shi:
Fast-yet-accurate PVT simulation by combined direct and iterative methods. ICCAD 2005: 495-501 - [c50]Bo Hu, Zhao Li, Lili Zhou, C.-J. Richard Shi, Kwang-Hyun Baek, Myung-Jun Choe:
Model-compiler based efficient statistical circuit analysis: an industry case study of a 4 GHz/6-bit ADC/DAC/DEMUX ASIC. ISCAS (6) 2005: 5621-5624 - [c49]Vikram Jandhyala, Yasuo Kuga, David J. Allstot, C.-J. Richard Shi:
Bridging Circuits and Electromagnetics in a Curriculum Aimed at Microelectronic Analog and Microwave Simulation and Design. MSE 2005: 45-46 - [c48]Roy Hartono, Nuttorn Jangkrajarng, Sambuddha Bhattacharya, C.-J. Richard Shi:
Automatic Device Layout Generation for Analog Layout Retargeting. VLSI Design 2005: 457-462 - 2004
- [j16]Sheldon X.-D. Tan, C.-J. Richard Shi:
Efficient approximation of symbolic expressions for analog behavioral modeling and analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(6): 907-918 (2004) - [c47]Zhao Li, Ravikanth Suravarapu, Roy Hartono, Sambuddha Bhattacharya, Kartikeya Mayaram, C.-J. Richard Shi:
CrtSmile: a CAD tool for CMOS RF transistor substrate modeling incorporating layout effects. ASP-DAC 2004: 163-168 - [c46]Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Roy Hartono, C.-J. Richard Shi:
Multiple specifications radio-frequency integrated circuit design with automatic template-driven layout retargeting. ASP-DAC 2004: 394-399 - [c45]Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, C.-J. Richard Shi:
Hierarchical extraction and verification of symmetry constraints for analog layout automation. ASP-DAC 2004: 400-405 - [c44]Guoyong Shi, C.-J. Richard Shi:
Parametric reduced order modeling for interconnect analysis. ASP-DAC 2004: 774-779 - [c43]Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, C.-J. Richard Shi:
Correct-by-construction layout-centric retargeting of large analog designs. DAC 2004: 139-144 - [c42]Bo Wan, C.-J. Richard Shi:
Hierarchical Multi-Dimensional Table Lookup for Model Compiler Based Circuit Simulation. DATE 2004: 1310-1315 - [c41]Zhao Li, C.-J. Richard Shi:
A coupled iterative/direct method for efficient time-domain simulation of nonlinear circuits with power/ground networks. ISCAS (5) 2004: 165-168 - [c40]Pavel V. Nikitin, Vikram Jandhyala, Daniel A. White, Nathan Champagne, John D. Rockway, C.-J. Richard Shi, Chuanyi Yang, Yong Wang, Gong Ouyang, Rob Sharpe, John W. Rockway:
Modeling and Simulation of Circuit-Electromagnetic Effects in Electronic Design Flow. ISQED 2004: 244-249 - [c39]Bo Wan, Pavel V. Nikitin, C.-J. Richard Shi:
Circuit level modeling and simulation of mixed-technology systems. SoCC 2004: 113-116 - 2003
- [j15]Sheldon X.-D. Tan, C.-J. Richard Shi:
Efficient DDD-Based Interpretable Symbolic Characterization of Large Analog Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3110-3118 (2003) - [j14]Sheldon X.-D. Tan, C.-J. Richard Shi:
Balanced multi-level multi-way partitioning of analog integrated circuits for hierarchical symbolic analysis. Integr. 34(1-2): 65-86 (2003) - [j13]Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Roy Hartono, C.-J. Richard Shi:
IPRAIL - intellectual property reuse-based analog IC layout automation. Integr. 36(4): 237-262 (2003) - [j12]Sheldon X.-D. Tan, C.-J. Richard Shi:
Efficient very large scale integration power/ground network sizing based on equivalent circuit modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(3): 277-284 (2003) - [j11]Sheldon X.-D. Tan, C.-J. Richard Shi, Jyh-Chwen Lee:
Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(12): 1678-1684 (2003) - [c38]Sheldon X.-D. Tan, C.-J. Richard Shi:
Efficient DDD-based term generation algorithm for analog circuit behavioral modeling. ASP-DAC 2003: 789-794 - [c37]Bo Wan, Bo P. Hu, Lili Zhou, C.-J. Richard Shi:
MCAST: an abstract-syntax-tree based model compiler for circuit simulation. CICC 2003: 249-252 - [c36]Alicia Manthe, Zhao Li, C.-J. Richard Shi:
Symbolic analysis of analog circuits with hard nonlinearity. DAC 2003: 542-545 - [c35]Alicia Manthe, Zhao Li, C.-J. Richard Shi, Kartikeya Mayaram:
Symbolic Analysis of Nonlinear Analog Circuits. DATE 2003: 11108-11109 - [c34]Lei Yang, C.-J. Richard Shi:
FROSTY: A Fast Hierarchy Extractor for Industrial CMOS Circuits. ICCAD 2003: 741-747 - [c33]Zhao Li, C.-J. Richard Shi:
SILCA: Fast-Yet-Accurate Time-Domain Simulation of VLSI Circuits with Strong Parasitic Coupling Effects. ICCAD 2003: 793-800 - [c32]Sambuddha Bhattacharya, C.-J. Richard Shi:
Concurrent logic and interconnect delay estimation of MOS circuits by mixed algebraic and Boolean symbolic analysis. ISCAS (4) 2003: 660-663 - [c31]Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Roy Hartono, C.-J. Richard Shi:
Automatic analog layout retargeting for new processes and device sizes. ISCAS (4) 2003: 704-707 - [c30]Pavel V. Nikitin, Winnie Yam, C.-J. Richard Shi:
Parametric Equivalent Circuit Extraction for VLSI Structures. VLSI-SOC 2003: 198-203 - 2002
- [c29]Vikram Jandhyala, Yong Wang, Dipanjan Gope, C.-J. Richard Shi:
Coupled Electromagnetic-Circuit Simulation of Arbitrarily-Shaped Conducting Structures Using Triangular Meshes. ISQED 2002: 38-42 - 2001
- [j10]C.-J. Richard Shi, Sheldon X.-D. Tan:
Compact representation and efficient generation of s-expandedsymbolic network functions for computer-aided analog circuit design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(7): 813-827 (2001) - [c28]Sheldon X.-D. Tan, C.-J. Richard Shi:
Fast Power/Ground Network Optimization Based on Equivalent Circuit Modeling. DAC 2001: 550-554 - [c27]